Data processor architecture

• US 4,523,290 A
• Filed: 10/25/1977
• Issued: 06/11/1985
• Est. Priority Date: 07/22/1974
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US06/844,765
• Time in Patent Office: 2,786 Days
• Field of Search: 364/862, 364/200 MS File, 364/900 MS File, 364/600, 364/602, 364/606, 364/607, 365/45, 365/222, 365/183, 365/103, 365/104, 365/1, 357/24, 328/167, 307/221 D, 333/165
• US Class Current: 708/3
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The present invention is directed to an improved data processor architecture. In a preferred embodiment, this architecture provides a hybrid stored program computer having analog and digital signals, where this architecture utilizes the combination of an integrated circuit analog read only memory, an integrated circuit analog alterable memory, and digital processing logic to achieve a low cost monolithic hybrid data processor. Analog CCD memories are provided for obtaining high capacity storage at low cost. Digital processing is provided for flexibility and capability. Analog to digital converters and digital to analog converters are used for communication between analog and digital portions of the data processor. Adaptive compensation having stored reference signals enhances analog signal precision.

Claims

1. A data processor system comprising:

an analog memory for storing a program, said analog memory including means for storing the program as a plurality of analog signals;

analog refresh circuitry for refreshing the analog signals stored in said analog memory;

accessing circuitry for accessing the program of stored analog signals from said analog memory; and

a stored program digital data processor for processing data under control of the program of stored analog signals accessed from said analog memory with said accessing circuitry.

2. The system as set forth in claim 1 above, wherein said stored program digital data processor includes a converter for converting the program accessed with said accessing circuitry to digital signal form and digital execution circuitry for processing the digital date in response to the stored program from said converter.

3. The system as set forth in claim 1 above, wherein said data processor includes an integrated circuit data processor, said integrated circuit data processor including

a. integrated circuit read only memory means for storing computer instructions in digital signal form and

b. integrated circuit execution means for processing the data in response to the stored digital computer instructions.

4. The system as set forth in claim 1 above, wherein said analog memory includes a charge coupled device for storing the analog signals in charge signal form and wherein said analog refresh circuitry includes analog bias refresh circuitry for reducing bias errors and analog scale factor refresh circuitry for reducing scale factor errors in the analog signals stored in said analog memory.

5. The system as set forth in claim 4 above, wherein said data processor is an integrated circuit data processor, said integrated circuit data processor including an integrated circuit read only memory for storing permanent information and an integrated circuit alterable memory for storing alterable information.

6. The system as set forth in claim 1 above, wherein said analog refresh circuitry includes an adaptive control circuit for processing the stored analog signals stored in said analog memory.

7. The system as set forth in claim 1 above, wherein said analog memory includes an analog read only memory for storing the program of signals in read only signal form;

said analog read only memory including means for storing the program of analog signals in electrode area form.

8. The system as set forth in claim 7 above, wherein said analog memory further includes an analog alterable memory for storing the data processed with said data processor in alterable analog signal form;

said data processor further including means for processing the data accessed from said analog alterable memory with said accessing circuitry under control of the program of stored analog signals.

9. The system as set forth in claim 1 above wherein said analog memory includes means for storing an analog reference signal and for storing an analog output signal, wherein said data processor includes a processing circuit for generating the analog output signal stored in said analog memory in response to the analog reference signal stored in said analog memory.

10. The system as set forth in claim 1 above, further comprising a digital to analog converter circuit for generating an analog input signal, wherein said data processor includes a circuit for generating an analog output signal in response to the analog input signal and the analog signals stored in said analog memory.

11. The system as set forth in claim 1 above, wherein said analog memory includes a nonvolatile analog memory for storing the program as a plurality of nonvolatile analog signals in nonvolatile signal form;

said data processor including means for processing the digital data under control of the program of stored nonvolatile analog signals accessed from said nonvolatile analog memory with said accessing circuitry.

12. The system as set forth in claim 11 above, wherein said analog memory further includes a volatile analog memory for storing volatile analog signals in volatile signal form;

said data processor further including means for processing the volatile analog signals accessed from said volatile analog memory with said accessing circuitry under control of the program of stored nonvolatile analog signals accessed from said nonvolatile analog memory with said accessing circuitry.

13. The system as set forth in claim 1 above, wherein said analog memory includes a nonvolatile analog memory for storing analog program signals and a volatile analog memory for storing alterable signals, wherein said stored program digital data processor includes means for processing the alterable signals stored in said volatile analog memory in response to the analog program signals stored in said nonvolatile analog memory.

14. The system as set forth in claim 1 above, wherein said system is a hybrid system, wherein said data processor includes a digital data processor for processing digital signals in response to the analog signals stored in said analog memory.

15. The system as set forth in claim 1 above, wherein said data processor includes a digital differential analyzer for processing incremental digital signals in response to the analog signals stored in said analog memory.

16. The system as set forth in claim 1 above, wherein said analog memory includes a nonvolatile analog sound memory for storing analog sound signals in electrode area form, said system further comprising a transducer for generating a sound in response to the analog sound signals stored in said nonvolatile analog sound memory.

17. The system as set forth in claim 1 above, wherein said system is a talking doll system and wherein said analog memory includes an analog speech memory for storing analog speech signals;

said system further comprising a transducer for generating a speech sound in response to the stored analog speech signals stored in said analog speech memory.

18. The system as set forth in claim 1 above, wherein said data processor program includes a plurality of analog program instructions and wherein said digital processing logic includes means for processing digital data under control of the data processor program instructions.

19. A stored program digital computer for processing digital data in response to a stored program, said digital computer comprising:

an analog main memory for storing a computer program in analog signal form;

accessing means for accessing the computer program stored in said analog main memory;

a digital operand memory for storing digital operands; and

digital processing logic for processing the digital operands stored in said digital operand memory under control of the computer program accessed from said analog main memory with said accessing means.

20. The system as set forth in claim 19 above, wherein said analog main memory includes an analog magnetic bubble main memory for storing the computer program in analog magnetic bubble signal form.

21. The system as set forth in claim 20 above, wherein the analog magnetic bubble signal form computer program stored in said analog magnetic bubble memory is stored in magnetic bubble analog size form, said analog magnetic bubble main memory including means for storing an analog magnetic bubble having a controlled analog size in said analog magnetic bubble main memory.

22. The system as set forth in claim 19 above, wherein said analog main memory includes means for storing the computer program as a plurality of electrode areas.

23. A data processor system for processing data in response to stored program instructions wherein said data processor comprises:

an analog main memory for storing program instructions in analog signal form;

means for accessing stored program instructions from said analog main memory; and

a stored program data processor for processing data in response to the program instructions accessed from said analog main memory with said accessing means.

24. The system as set forth in claim 23 above, wherein said analog main memory includes means for storing the computer program instructions as electrode areas.

25. A memory system comprising:

an analog memory for storing analog signals;

an analog refresh circuit for refreshing the analog signals stored in said analog memory;

an analog to digital converter for generating digital signals in response to the stored analog signals from said analog memory;

a digital processor for processing the digital signals generated with said converter; and

a digital to analog converter for generating analog signals in response to the digital signals processed with said digital processor;

wherein said analog memory includes means for storing the analog signals generated with said digital to analog converter.

26. The system as set forth in claim 25 above, wherein said analog memory includes means for storing the analog signals as a plurality of electrode areas.

27. The system as set forth in claim 25 above, wherein the analog signals stored in said analog memory include a plurality of program instructions, wherein said digital processor is a stored program digital processor, and wherein said stored program digital processor includes means for processing the digital signals generated with said analog to digital converter under control of the program instructions.

28. A data processor system comprising:

an analog memory for storing analog information, wherein said analog memory includes

(a) a nonvolatile memory for storing analog information in nonvolatile signal form,

(b) a volatile memory for storing analog information in volatile signal form,

(c) a read only memory for storing analog information in read only signal form,

(d) an alterable memory for storing analog information in alterable signal form,

(e) adaptive control circuitry for adaptively controlling storage of analog information, and

(f) shift circuitry for shifting stored analog information;

a digital memory for storing digital information, said digital memory including

(a) a nonvolatile digital memory for storing digital information in nonvolatile signal form,

(b) a volatile digital memory for storing digital information in volatile signal form,

(c) a digital read only memory for storing permanent digital information, and

(d) an alterable digital memory for storing alterable digital information;

accessing circuitry for accessing stored information, said accessing circuitry including

(a) analog online accessing circuitry for accessing analog information stored in said analog memory as online analog information,

(b) analog offline accessing circuitry for accessing the analog information stored in said analog memory for offline processing,

(c) online digital accessing circuitry for accessing digital information stored in said digital memory for online processing,

(d) offline digital accessing circuitry for accessing digital information stored in said digital memory for offline processing,

(e) a converter for generating digital accessed information in response to the analog information accessed from said analog memory,

(f) analog block accessing circuitry for accessing a block of analog information stored in said analog memory, and

(g) digital block accessing circuitry for accessing a block of digital information stored in said digital memory;

a stored program data processor for processing information in response to a stored program, said data processor including

(a) a first processor for processing analog information stored in said analog memory in response to an analog program stored in said analog memory,

(b) a second processor for processing digital information stored in said digital memory in response to an analog program stored in said analog memory,

(c) a third processor for processing analog information stored in said analog memory in response to a digital program stored in said digital memory, and

(d) a fourth processor for processing digital information stored in said digital memory in response to a digital program stored in said digital memory; and

a special purpose data processor, said special purpose data processor including

(a) a fifth data processor for generating analog output information in response to analog information stored in said analog memory,

(b) a sixth data processor for generating digital output information in response to analog information stored in said analog memory,

(c) a seventh data processor for generating analog output information in response to digital information stored in said digital memory, and

(d) an eighth data processor for generating digital output information in response to digital information stored in said digital memory.

29. A stored program computer comprising:

an analog program memory for storing program instructions;

means for accessing program instructions from said analog program memory;

an operand memory for storing an operand;

a digital processor for processing the operand stored in said operand memory in response to the program instructions accessed from said analog program memory with said accessing means.

30. The computer as set forth in claim 29 above, wherein said analog program memory includes an analog charge coupled device read only memory for storing the program instructions in analog electrode size form.

31. The computer as set forth in claim 29 above, wherein said analog program memory includes an analog magnetic bubble memory for storing the program instructions in analog magnetic bubble form.

32. The computer as set forth in claim 29 above, wherein said computer is an integrated circuit computer, wherein said analog program memory includes an integrated circuit analog read only memory for storing the program instructions in analog read only form and wherein said operand memory includes an integrated circuit alterable memory for storing a plurality of operands in alterable form.

33. The computer as set forth in claim 29 above, wherein said analog program memory includes an adaptive control circuit for processing the analog program instructions stored therein.

34. The computer as set forth in claim 29 above, wherein said analog program memory includes an analog read only memory having an electrode area information content for storing the program in read only signal form and wherein said operand memory includes an analog alterable memory for storing the operand in analog signal form.

35. The computer as set forth in claim 29 above, wherein said analog program memory includes means for storing the program as a plurality of computer instructions.

36. The computer as set forth in claim 29 above, wherein said analog program memory includes means for storing an analog reference signal and means for storing analog program instruction signals, wherein said computer includes a refresh circuit for refreshing the analog program instruction signals stored in said analog program memory in response to the analog reference signal stored in said analog program memory.

37. The computer as set forth in claim 29 above, wherein said operand memory is an analog operand memory, wherein said analog operand memory includes means for storing the operand in analog signal form, means for storing an analog reference signal, and a refresh circuit for refreshing the stored operand in response to the analog reference signal.

38. The computer as set forth in claim 29 above, wherein said analog program memory includes a nonvolatile analog memory for storing the program instructions in nonvolatile signal form.

39. The computer as set forth in claim 38 above, wherein said operand memory includes a volatile analog memory for storing an analog operand in volatile signal form.

40. The computer as set forth in claim 29 above, wherein said analog program memory includes a sound memory for storing analog sound information, said computer further comprising a transducer for generating a sound in response to the analog sound information stored in said analog program memory.

41. The computer as set forth in claim 29 above, wherein said analog program memory includes an analog speech memory for storing analog speech information, said computer further comprising a transducer for generating a speech sound in response to the stored analog speech information.

42. A stored program analog computer comprising:

an analog main memory for storing a program in analog signal form;

accessing means for accessing the program stored in said analog main memory;

an analog scratched memory for storing an operand in analog signal form; and

analog circuitry for processing the operand stored in analog signal form in said analog scratchpad memory in response to the program accessed from said analog main memory with said accessing means.

43. A stored program hybrid computer comprising:

an analog program memory for storing a program in analog signal form;

accessing means for accessing the program from said analog program memory;

a digital operand memory for storing an operand in digital signal form; and

a stored program digital processor for processing the operand stored in said digital operand memory in digital signal form in response to the program accessed from said analog program memory in analog signal form.

44. A stored program computer system comprising:

an analog program memory for storing a computer program as a plurality of analog signals;

means for accessing the computer program from said analog program memory;

an operand memory for storing a computer operand; and

a stored program computer for processing the computer operand stored in said operand memory in response to the computer program accessed from said analog program memory.

45. The system as set forth in claim 44 above, wherein said analog program memory includes an electrical charge memory for storing the analog signals in charge signal form.

46. The system as set forth in claim 44 above, wherein said stored program computer is an analog stored program computer and wherein said operand memory is an analog operand memory for storing the computer operand in analog signal form, said analog computer including means for processing the operand stored in said analog operand memory in response to the computer program stored in said analog program memory.

47. The system as set forth in claim 44 above, wherein said analog program memory includes a magnetic bubble memory for storing the computer program in analog magnetic bubble signal form.

48. The system as set forth in claim 44 above, wherein said analog program memory includes an integrated circuit read only memory for storing permanent analog information and wherein said operand memory includes an integrated circuit analog alterable memory for storing alterable analog operands.

49. The system as set forth in claim 44 above, wherein said analog program memory includes an adaptive control circuit for processing the stored analog signals.

50. The system as set forth in claim 44 above, wherein said analog program memory includes an analog read only memory for storing the analog signals in electrode area form.

51. The system as set forth in claim 50 above, wherein said operand memory includes an analog alterable memory for storing the computer operand as an analog signal in alterable signal form.

52. The system as set forth in claim 44 above, wherein said analog program memory is a computer main memory.

53. The system as set forth in claim 44 above, wherein said analog program memory includes means for generating a reference signal, means for storing the reference signal, and means for refreshing the stored analog signals in response to the stored reference signal.

54. The system as set forth in claim 44 above, further comprising an input circuit for generating an analog input signal, wherein said computer includes a circuit for generating an analog output signal in response to the analog input signal under control of the analog signals stored in said analog program memory.

55. The system as set forth in claim 44 above, wherein said analog program memory includes a refresh circuit for refreshing the stored analog signals to reduce scale factor degradation of the stored analog signals.

56. The system as set forth in claim 44 above, wherein said analog program memory includes a nonvolatile analog memory for storing the analog signals in electrode area form.

57. The system as set forth in claim 44 above, wherein said analog program memory further includes a volatile analog memory for storing the analog signals in volatile signal form.

58. The system as set forth in claim 44 above, wherein said analog program memory includes a nonvolatile analog memory for storing analog program signals and wherein said operand memory includes a volatile analog memory for storing the operand in alterable signal form, wherein said computer includes a processor for processing the alterable signals stored in said volatile analog memory in response to the analog program signals stored in said analog program memory.

59. The system as set forth in claim 44 above, wherein said system is a hybrid system, wherein said computer includes a digital data processor for processing digital information in response to the computer program stored in said analog program memory.

60. The system as set forth in claim 44 above, wherein said analog program memory includes a sound memory for storing analog sound information, said system further comprising a transducer for generating a sound in response to the analog sound information stored in said analog program memory.

61. The system as set forth in claim 45 above, wherein said system is a talking doll system, wherein said analog program memory includes an analog speech memory for storing analog speech information, wherein said system further comprises a transducer for generating speech information in response to the stored analog speech information.

62. The system as set forth in claim 44 above, wherein said operand memory is a digital operand memory for storing a digital operand and wherein said stored program computer includes means for processing the digital operand stored in said operand memory in response to the computer program stored in said analog program memory.

63. A data processor system comprising:

a magnetic bubble memory for storing analog information in magnetic bubble form, wherein the analog information includes analog program information, and wherein said magnetic bubble memory is a data processor main memory;

accessing circuitry for accessing the stored analog information from said magnetic bubble memory in response to an access signal, wherein the analog information accessed with said accessing circuitry is analog program information; and

a data processor for generating the access signal, wherein said data processor is a stored program data processor for processing data in response to the analog program information accessed from said main memory with said accessing circuitry.