Microcomputer retriggerable interval counter
First Claim
1. A microcomputer having an interval counter for timing the duration between successive input signals so as to provide a maskable output interrupt signal which is indicative of said time duration and to which said microcomputer is responsive, said interval counter comprising:
- receiving means for storing a preset count number corresponding to a preset time duration;
counting means for periodically decrementing a count number and producing said output interrupt signal when said count number is fully decremented and when the time interval between said input signals exceeds the count number; and
control means responsive to the receipt of said input signals in order to cause said preset count number to be transferred from said receiving means to said counting means.
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Accused Products
Abstract
A microcomputer interval counter circuit for detecting the time interval between input signals and for determining when the detected time interval exceeds a preset time interval.
The interval counter circuit includes a latch connected to a bus of the microcomputer for storing the preset time interval duration, a counter circuit connected to the latch and to the microcomputer clock for decrementing a number stored in the counter and producing a timing indication as an interrupt to the microcomputer processor, and an OR gate connected to load the counter from the latch when an input signal is received, or when the counter circuit fully decrements.
40 Citations
20 Claims
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1. A microcomputer having an interval counter for timing the duration between successive input signals so as to provide a maskable output interrupt signal which is indicative of said time duration and to which said microcomputer is responsive, said interval counter comprising:
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receiving means for storing a preset count number corresponding to a preset time duration; counting means for periodically decrementing a count number and producing said output interrupt signal when said count number is fully decremented and when the time interval between said input signals exceeds the count number; and control means responsive to the receipt of said input signals in order to cause said preset count number to be transferred from said receiving means to said counting means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A microcomputer having a central processor for executing instructions, memory for storing data and instructions, and a data bus for transferring information, wherein the improvement comprises an interval counter for measuring the time interval between successive input signals and providing a maskable output interrupt signal which is indicative of the time interval measured and to which said processor is responsive, said interval counter comprising:
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receiving means for receiving initialization information from said data bus; counting means for producing said output interrupt signal in response to said input signals and after a duration specified by said initialization information, and for providing said output interrupt signal to said processor; and control means connected to control said receiving means and said counting means so that when said output interrupt signal is received from said counting means, said control means initializes said counting means by automatically transferring said initialization information from said receiving means to said counting means. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An interval counter microcomputer for measuring the interval between successive input signals, said microcomputer comprising:
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counting means for producing a timing indication when the time interval between successive input signals exceeds a preset time interval, said counting means repeatedly decrementing a preset count number which corresponds to said preset time interval and which has become fully decremented during the time interval between said input signals; and processor means responsive to said timing indication for determining the interval between successive input signals. - View Dependent Claims (20)
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Specification