Semiconductor memory

• US 4,539,658 A
• Filed: 08/08/1984
• Issued: 09/03/1985
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo, Ikuzaki, Kunihiko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/638,982
• Time in Patent Office: 391 Days
• Field of Search: 365/174, 365/182, 365/189, 365/207, 365/203, 365/230
• US Class Current: 365/207
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory comprising:

a plurality of pairs of data lines;

differential amplifiers, each of which amplifies a difference between signal levels appearing on each pair of data lines;

word lines, each of which is arranged so as to intersect with each pair of data lines; and

precharging circuits, each of which sets each pair of data lines at a potential intermediate between binary signal levels to be stored in memory cells, before operation of the corresponding differential amplifier is started.