Digital filtering system

• US 4,553,221 A
• Filed: 09/27/1982
• Issued: 11/12/1985
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US06/423,961
• Time in Patent Office: 1,142 Days
• Field of Search: 364/724, 364/725, 364/728, 364/421
• US Class Current: 708/308
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A digital filtering system is provided for acquiring and processing signals using a digital filter for signal separation and signal enhancement. A digital correlator is provided for generating high resolution output data in response to low resolution input data processed with low resolution computational circuits. In one embodiment, a real-time time-domain correlator is provided with single-bit resolution computational elements to implement the correlation filtering operation. Use of the high speed real-time correlator of the present invention permits further enhancement of signals with the capability of compositing-after-correlation and with the capability of correlation using a plurality of correlation operators. Particular advantages are achieved with the use of the real-time correlator in a geophysical exploration system embodiment and in a communication embodiment. Systems applications of the digital filter includes a communications modem for modulating and demodulating chirp signals to enhance data communication and compositing-after-correlation in a geophysical exploration system. Detailed circuitry is provided to implement such systems including an improved chirp signal generator, a multi-chirp signal generator, a chirp modulator, and a correlation demodulator.

Claims

1. A filter system comprising:

means for generating single bit input signal samples and

a filter processor for generating multibit filtered output signal samples in response to the single bit input signal samples.

2. The system as set forth in claim 1 above, further comprising seismic signal generating means for generating an output seismic signal to propogate through the ground, wherein the input signal samples are related to reflections of the output seismic signal from underground structures.

3. The system as set forth in claim 1 above, wherein said single bit input signal sample generating means includes means for generating the single bit input signal samples as input single bit spacial signal samples, wherein said incremental processor includes

reference means for generating reference signal samples,

analog multiplying means for generating analog product signal samples by multiplying the input signal samples and the reference signal samples on the fly,

analog summing means for generating the filtered output signal samples as analog filtered output signal samples having improved signal to noise ratio by summing the analog product signal samples, wherein the filtered output signal samples represent geophysical information, and wherein said incremental processor further includes means for generating the filtered output signal samples as correlation filtered output signal samples;

and

a charge coupled device memory for storing the analog filtered output signals generated with said analog summing means.

4. A geophysical exploration system comprising:

seismic input means for generating an input seismic signal related to geophysical exploration of underground structures;

input signal generating means for generating incremental input signal samples in response to the geophysical exploration-related input seismic signal; and

an incremental processor for generating a geophysical exploration underground structure-related processor signal in response to the incremental input signal.

5. A filter system comprising:

means for generating an incremental input signal and

an incremental discrete Fourier transform processor for generating a frequency-related filtered signal in response to the incremental input signal.

6. A filter system comprising:

means for generating an incremental input signal and

a correlation processor for generating a correlation processed filtered signal in response to the incremental input signal.

7. A filter system comprising:

input means for generating incremental input signal samples and

an incremental processor for generating filtered output signal samples in response to the incremental input signal samples, wherein said incremental processor includes

(a) reference means for generating reference signal samples;

(b) memory means for storing filtered signal samples;

(c) multiplying means for generating product signal samples by multiplying the incremental input signal samples generated with said input means and the reference signal samples generated with said reference means; and

(c) update means for updating the filtered signal samples stored in said memory means in response to the incremental input signal samples generated with said input means.

8. A spacial filter system comprising:

spacial input means for generating single bit spacial input signal samples and

a spacial filter processor for generating filtered spacial output signal samples in response to the single bit spacial input signal samples generated with said spacial input means, wherein said spacial filter processor includes

reference means for generating spacial reference signal samples;

output means for storing spacial output signal samples; and

update means for updating the spacial output signal samples in response to the single bit spacial input signal samples generated with said spacial input means, said update means including

(a) product means for generating product signal samples by multiplying the single bit spacial input signal samples generated with said spacial input means and the reference signal samples generated with said reference means and

(b) summing means for adding the product signal samples generated with said product means and the spacial output signal samples stored with said output means.

9. A filter system comprising:

input means for generating a plurality of incremental input signal samples and

a digital incremental processor for generating a plurality of higher resolution multibit filtered output signal samples in response to the lower resolution incremental input signal samples generated with said input means, wherein said incremental processor includes;

(a) reference means for generating reference signal samples,

(b) multiplying means for generating product signal samples by multiplying the incremental input signal samples generated with said input means and the reference signal samples generated with said reference means, and

(c) summing means for generating the higher resolution multibit filtered output signal samples by summing the product signal samples generated with said multiplying means.

10. The system as set forth in claim 9 above, further comprising:

memory means for storing the higher resolution multibit filtered output signal samples as the higher resolution multibit filtered output signal samples are generated with said summing means and

means for outputting the higher resolution multibit filtered output signal samples simultaneously with generation of the higher resolution multibit filtered output signal samples with said summing means.

11. A filter system comprising:

input means for generating input signal samples and

an on the fly filter processor for generating a filtered output signal in response to the input signal samples generated with said input means by on the fly processing.

12. A filter system comprising:

input means for generating a plurality of incremental input signal samples and

an incremental processor for generating filtered output signal samples in response to the incremental input signal samples generated with said input means, wherein said incremental processor includes

(a) reference means for generating reference signal samples,

(b) multiplying means for generating product signal samples by multiplying each of the input signal samples generated with said input means by a plurality of reference signal samples generated with said reference means before multiplying a next input signal sample by a reference signal sample, and

(c) summing means for generating the filtered output signal samples by summing the product signal samples generated with said multiplying means.

13. A filter system comprising:

input means for generating a plurality of input signal samples;

reference means for generating reference signal samples;

multiplying means for generating product signal samples by multiplying the input signal samples generated with said input means and the reference signal samples generated with said reference means, wherein said multiplying means includes means for fully processing an input single sample prior to processing the next input signal sample; and

summing means for generating filtered output signal samples by summing the product signal samples generated with said multiplying means.

14. A filter system comprising:

input means for generating incremental input signal samples;

an output memory for storing filtered output signal samples; and

an incremental processor for updating the filtered output signal samples stored in said output memory in response to the incremental input signal samples generated with said input means, wherein said incremental processor includes;

(a) reference means for generating reference signal samples,

(b) multiplying means for generating product signal samples by multiplying the input signal samples generated with said input means and the reference signal samples generated with said reference means, and

(c) updating means for updating the filtered output signal samples stored in said output memory in response to the product signal samples generated with said multiplying means.

15. A filter system comprising:

input means for generating input signal samples;

an output memory for storing filtered signal samples; and

a filter processor for updating the filtered signal samples stored in said output memory in response to the input signal samples generated with said input means, wherein said processor includes;

(a) reference means for generating reference signal samples,

(b) multiplying means for generating product signal samples by multiplying the input signal samples generated with said input means and the reference signal samples generated with said reference means, and

(c) summing means for updating the filtered signal samples stored in said output memory by summing the product signal samples generated with said multiplying means with the filtered signal samples stored in said output memory; and

means for outputting the filtered signal samples stored in said output memory while the generation of the filtered signal samples is being performed with said summing means.

16. A filter system comprising:

spacial input means for generating spacial incremental input signal samples;

a spacial incremental processor for generating filtered spacial output signal samples in response to the spacial incremental input signal samples generated with said spacial input means; and

a memory for storing the filtered spacial output signal samples generated with said spacial incremental processor.

17. A spacial filter system comprising:

incremental spacial input means for generating a plurality of channels of incremental spacial input signal samples and

a plurality of channels of spacial incremental processors, wherein each channel of spacial incremental processors includes filter means for generating a channel of filtered spacial output signal samples in response to a related channel of incremental spacial input signal samples generated with said incremental spacial input means and wherein each channel of spacial incremental processors includes

(a) reference means for generating spacial reference signal samples and

(b) multiplying means for generating spacial product signal samples by multiplying the incremental spacial input signal samples of the related channel generated with said spacial input means and the spacial reference signal samples generated with said reference means of the related channel; and

summing means for generating multiple channel filtered spacial output signals samples by summing the spacial product signal samples generated with a plurality of multiplying means each included in a different one of the plurality of channels of spacial incremental processors.

18. A filter system comprising:

input means for generating input signal samples;

a filter processor for generating filtered signal samples in response to the input signal samples generated with said input menas;

output means for successively outputting the filtered signal signal samples generated with said filter processor; and

means for building up the magnitude of the filtered signal samples generated with said filter processor as the filtered signal samples are successively output.

19. A filter system comprising:

input means for generating a plurality of input signal samples and

a filter processor for generating a plurality of filtered output signal samples in response to the input signal samples generated with said input means, wherein said filter processor includes;

(a) reference means for generating reference signal samples,

(b) multiplying means for generating a plurality of product signal samples by multiplying a plurality of reference signal samples generated with said reference means by a single input signal sample generated with said input means before multiplying a reference signal sample generated with said reference means by another input signal sample generated with said input means, and

(c) summing means for generating the filtered output signal samples by summing the product signal samples generated with said multiplying means.

20. A filter system comprising:

input means for generating input signal samples;

reference means for generating reference signal samples;

multiplying means for generating product signal samples by multiplying the input signal samples generated with said input means and the reference signal samples generated with said reference means;

output means for generating filtered output signal samples in response to the product signal samples generated with said multiplying means; and

means for increasing signal to noise ratio of the output signal samples generated with said output means.

21. A filter system comprising

input means for generating a plurality of incremental input signal samples and

an incremental processor for generating filtered signal samples in response to the incremental input signal samples generated with said input means, wherein said incremental processor includes

(a) a memory for storing the filtered signal samples,

(b) accessing means for accessing filtered signal samples stored in said memory,

(c) reference means for generating reference signal samples,

(d) multiplying means for generating product signal samples by multiplying the input signal samples generated with said input means and the reference signal samples generated with said reference means,

(e) update means for updating the filtered signal samples accessed with said accessing means by summing the product signal samples generated with aid multiplying means with the filtered output signal samples accessed with said accessing means,

(f) outputting means for outputting the updated filtered signal samples, and

(g) loading means for loading the filtered signal samples updated with said update means into said memory.

22. A filter system comprising:

a plurality of spacial domain filter processors for generating filtered signal samples, wherein each of the spacial domain filter processors includes

(a) input means for generating input signal samples,

(b) reference means for generating reference signal samples, and

(c) multiplying means for generating product signal samples by multiplying the input signal samples generated with said input means by reference signal samples generated with said reference means;

summing means for generating filtered spacial signal samples by summing product signal samples generated with a plurality of said multiplying means from said plurality of spacial domain filter processors;

a memory for storing the filtered spacial signal samples generated with said summing means; and

output means for outputting the filtered spacial signal samples stored in said memory.

23. A filter processor system comprising:

input means for generating a plurality of input signal samples;

reference means for storing reference signal samples;

output means for storing filtered signal samples; and

update means for updating the filtered signal samples stored in said output means in response to each of a plurality of input signal samples as the input signal samples are generated with said input means, said update means including product means for generating a plurality of product signal samples by multiplying an input signal sample and a plurality of reference signal samples and summing means for updating the filtered signal samples stored in said output means by adding the product signal samples generated with said product means to the filtered signal samples stored in said output means.

24. The system as set forth in claim 23 above, wherein said update means includes an on the fly filter processor for processing the input signal samples on the fly.

25. The system as set forth in claim 23 above, wherein said product means includes means for generating the plurality of product signal samples by multiplying each of the input signal samples and a plurality of reference signal samples before multiplying a next input signal sample and a reference signal sample.

26. The system as set forth in claim 23 above;

wherein said product means includes means for fully processing an input signal sample with said product means prior to processing the next input signal sample with said product means.

27. The system as set forth in claim 23 above, wherein said summing means includes means for updating the filtered signal samples stored in said output means by adding each of the product signal samples generated with said product means to at least one of the filtered signal samples stored in said output means for outputting of the filtered signal samples while the updating of the filtered signal samples is being performed with said summing means.

28. The system are set forth in claim 23 above, wherein said summing means includes means for updating the filtered signal samples stored in said output means by adding each of the product signal samples generated with said product means to at least one of the filtered signal samples stored in said output means and means for generating the filtered signal samples stored in said output means as composited filtered signal samples by compositing the filtered signal samples.

29. The system as set forth in claim 23 above, further comprising:

means for successively outputting the filtered signal samples stored in said output means and

means for building up resolution of the filtered signal samples stored in said output means as the filtered signal samples stored in said output means are successively output with said successively outputting means.

30. The system as set forth in claim 23 above, further comprising means for outputting the filtered signal samples stored in said output means simultaneously with the updating of the filtered signal samples with said summing means.

31. The system as set forth in claim 23 above, further comprising means for accessing filtered signal samples stored in said output means, wherein said summing means includes means for updating the filtered signal samples accessed with said accessing means and means for outputting the filtered signal samples updated with said summing means.

32. A filter system comprising:

input means for generating single bit resolution digital input signal samples;

reference means for generating reference signal samples;

output means for storing multibit resolution digital filtered signal samples; and

update means for updating the multibit resolution digital filtered signal samples stored in said output means in response the single bit resolution digital input signal samples generated with said input means, said update means including (a) product means for generating product signal samples by multiplying the single bit resolution input signal samples generated with said input means and the reference signal samples generated with said reference means and (b) summing means for updating the multibit resolution digital filtered signal samples stored in said output means by adding the product signal samples generated with said product means to the multibit resolution digital filtered signal samples stored in said output means.

33. A filter system comprising:

input means for generating input signal samples;

reference means for storing single bit resolution digital reference signal samples;

output means for storing multibit resolution digital filtered signal samples; and

update means for updating the multibit resolution digital filtered signal samples stored in said output means in response the input signal samples generated with said input means, said update means including (a) product means for generating a plurality of product signal samples by multiplying the input signal samples generated with said input means and the single bit resolution digital reference signal samples generated with said reference means and (b) summing means for updating the multibit resolution digital filtered signal samples stored in said output means by adding the product signal samples generated with said product means to the multibit resolution digital filtered signal samples stored in said output means.

34. A digital processor system comprising:

input means for generating input signal samples;

reference means for generating reference signal samples;

output means for storing output signal samples; and

update means for updating the output signal samples stored in said output means in response to the input signal samples, said update means including

(a) product means for generating product signal samples by multiplying input signal samples and reference signal samples and

(b) summing means for updating the output signal samples stored in said output means to have better digital resolution then said input signal samples by adding the product signal samples to the output signal samples.

35. A correlation filter system comprising:

input means for generating input signal samples;

reference means for generating reference signal samples;

output means for storing correlation filtered signal samples; and

update means for updating the correlation filtered signal samples stored in said output means in response to the input signal samples generated with said input means, said update means including product means for generating a plurality of product signal samples by multiplying the input signal samples generated with said input means and reference signal samples generated with said reference means and summing means for updating the correlation filtered signal samples stored in said output means by adding the product signal samples generated with said product means to the correlation filtered signal samples stored in said output means.

36. A spacial filter system comprising:

spacial input means for generating input spacial signal samples;

reference means for generating reference signal samples;

a memory for storing filtered spacial signal samples; and

spacial update means for updating the filtered spacial signal samples stored in said memory in response to the input spacial signal samples generated with said spacial input means, said spacial update means including spacial product means for generating spacial product signal samples by multiplying input spacial signal samples generated with said spacial input means and reference signal samples generated with said reference means and summing means for updating the filtered spacial signal samples stored in said memory by adding the spacial product signal samples generated with said product means to the filtered spacial signal samples stored in said memory.

37. The system as set forth in claim 36 above, wherein said memory includes means for outputting the filtered spacial signal samples stored therein and means for updating of the filtered spacial output signal samples stored therein at the same time that the output signal samples stored therein are being output.

38. A filter processor system comprising:

input means for generating input signal samples;

reference means for generating reference signal samples;

output means for storing filtered signal samples; and

update means for updating the filtered signal samples stored in said output means in response to each of a plurality of input signal samples generated with said input means as the input signal samples are generated with said input means, said update means including

(a) product means for multiplying each of a plurality of reference signal samples generated with said reference means by a single input signal sample to generate a plurality of product signal samples before multiplying a reference signal sample by a next input signal sample and

(b) summing means for adding the product signal samples generated with said product means to the filtered signal samples stored in said output means.

39. A filter processor system comprising:

input means for generating input signal samples;

reference means for generating reference signal samples;

output means for storing output signal samples; and

update means for updating the output signal samples in response to the input signal samples generated with said input means, said update means including

(a) product means for generating product signal samples by multiplying input signal samples and reference signal samples and

(b) summing means for updating the output signal samples stored in said output means by adding the product signal samples to the output signal samples to cause the output signal samples to increase in signal to noise ratio.

40. A signal processor system comprising:

input means for generating an input signal having a plurality of signature components and

a signal processor for generating a plurality of output signals in response to the input signal, said signal processor including means for processing the input signal with each of a plurality of signature signals to separate out the signature components of the input signal to generate the plurality of output signals.

41. The system as set forth in claim 40 above, wherein said input means includes means for generating the input signal having a plurality of multiplexed chirp signature components.

42. A signal processor system comprising:

input means for generating an input signal having a plurality of signature components and

a correlator processor for generating a plurality of correlated output signals in response to the input signal, said correlator processor including means for correlating the input signal with each of a plurality of signature components to seperate out the signature components of the input signal to generate the plurality of output signals.