Multiprocessor computer system
First Claim
1. A multiprocessing computer system comprising:
- (A) a plurality of central processing systems, each system including(a) at least one central processing unit for processing data in response to instructions and having the capability to produce address source information,(b) memory means for storing data,(c) bus means for transferring data between said at least one central processing unit and said memory means,(d) intermemory link adaptor means connected to said bus means for transporting data externally of said central processing system; and
(e) DMA means associated with said intermemory link adaptor means for producing address source information and for controlling transfers of data via said intermemory link adaptor means and said bus means to and from said memory means without intervention by said at least one central processor unit,(B) at least a portion of said memory means defining a common memory having separate port means for connecting via respective bus means at least two of said plurality of central processing systems, said separate port means causing said common memory to be shared by the two central processing systems;
(C) at least part of said common memory being compartmentalized and divided into a number of separate memory compartments wherein each of said memory compartments is coupled to a respective data transfer port and to said respective bus means of at least two of said plurality of central processing systems;
(D) at least one peripheral device controller means associated with at least one of said plurality of central processing systems and being adapted for connection with a peripheral device, each said peripheral device controller means being connected to a preselected memory compartment of said common memory via the data transfer port associated with said preselected memory compartment, said peripheral device controller means having means for producing and means for responding to address source information and means for controlling the transfer data between said peripheral device and the preselected memory compartment of said common memory;
(E) an intermemory communication network comprising a plurality of intermemory link means for connection with said intermemory link adaptor means of said plurality of central processing systems and for transferring data among said memory means of respective ones of said plurality of central processing systems; and
(F) DMA interface controller means connected to said intermemory communication network via said intermemory link adaptor means, said DMA interface controller means for controlling access to said memory of each of said plurality of central processing systems via said DMA means, said DMA interface controller means multiplexing transfers of data over said intermemory communication network, said DMA interface controller means being further operative to effect logical connection of at least two intermemory link adaptor means of respective ones of said central processing systems to said intermemory communication network in response to said address source information and to multiplex transfers of data among said memory means of the respective central processing systems over said intermemory communication network without intervention by said associated central processing unit.
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Accused Products
Abstract
A multiprocessor computer system wherein memory buses of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems.
The intermemory communication network includes a plurality of preferably passive intermemory communication links being tapped for connection to link adapters interfacing a number of central processing unit systems to each intermemory communication link. The number of central processing unit systems may be different for different intermemory communication links.
The memory buses are configurated to allow for direct data transfer between any memory fraction of a common memory shared by at least two central processing unit systems without interfering with the central processing units such that the data transfer is controlled by direct memory access control means.
The multiprocessor computer system includes separate configuration controllers being effective to reconfigurate the overall system in the event of failure. The reconfiguration comprises switching of fractions of memory between the memory buses of at least two central processing unit systems. At least one of the memory fractions is directly addressable by a respective peripheral processor. Also, one of the peripheral processors backs up the others to obtain N+1 redundancy.
171 Citations
30 Claims
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1. A multiprocessing computer system comprising:
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(A) a plurality of central processing systems, each system including (a) at least one central processing unit for processing data in response to instructions and having the capability to produce address source information, (b) memory means for storing data, (c) bus means for transferring data between said at least one central processing unit and said memory means, (d) intermemory link adaptor means connected to said bus means for transporting data externally of said central processing system; and (e) DMA means associated with said intermemory link adaptor means for producing address source information and for controlling transfers of data via said intermemory link adaptor means and said bus means to and from said memory means without intervention by said at least one central processor unit, (B) at least a portion of said memory means defining a common memory having separate port means for connecting via respective bus means at least two of said plurality of central processing systems, said separate port means causing said common memory to be shared by the two central processing systems; (C) at least part of said common memory being compartmentalized and divided into a number of separate memory compartments wherein each of said memory compartments is coupled to a respective data transfer port and to said respective bus means of at least two of said plurality of central processing systems; (D) at least one peripheral device controller means associated with at least one of said plurality of central processing systems and being adapted for connection with a peripheral device, each said peripheral device controller means being connected to a preselected memory compartment of said common memory via the data transfer port associated with said preselected memory compartment, said peripheral device controller means having means for producing and means for responding to address source information and means for controlling the transfer data between said peripheral device and the preselected memory compartment of said common memory; (E) an intermemory communication network comprising a plurality of intermemory link means for connection with said intermemory link adaptor means of said plurality of central processing systems and for transferring data among said memory means of respective ones of said plurality of central processing systems; and (F) DMA interface controller means connected to said intermemory communication network via said intermemory link adaptor means, said DMA interface controller means for controlling access to said memory of each of said plurality of central processing systems via said DMA means, said DMA interface controller means multiplexing transfers of data over said intermemory communication network, said DMA interface controller means being further operative to effect logical connection of at least two intermemory link adaptor means of respective ones of said central processing systems to said intermemory communication network in response to said address source information and to multiplex transfers of data among said memory means of the respective central processing systems over said intermemory communication network without intervention by said associated central processing unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. In a multiprocessing computer system, a central processing system comprising:
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a plurality of central processing units processing data in response to instructions and having means for producing address source information, memory means for storing data, a plurality of address sourcing devices other than said plurality of central processing units producing address source information for transferring and storing data, first bus means associated with said plurality of central processing units and with a first portion of said memory means for transferring data among said plurality of central processing units and said memory means along a first memory path, second bus means for connecting said plurality of address sourcing devices along a second memory path to said first portion of said memory means, and for connecting said at least one central processing unit and at least one of said plurality of said address sourcing devices along a third common extension path to a second portion of said memory means, said first and second memory paths enabling said at least one central processing unit and said at least one address sourcing devices to access said first portion of said memory means without contention, and being effective to reduce contention among each other when accessing said second portion of said memory means, intermemory link adaptor means connected to said second bus means for transferring data externally of said central processing system to and from the memory means of selected ones of said plurality of central processing systems, and DMA interface controller means cooperating with the producer of said address source information for controlling external transfers of data via said intermemory link adaptor means, so as to provide decreased contention between respective memory means in said central processing system and in the external central processing system. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A central processing system comprising:
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at least one central processing unit having means for processing data in response to instructions and having means for producing address source information, memory means for storing data, bus means interconnecting said memory means and said central process unit, one or more address sourcing devices in addition to said central processing unit including means for controlling transfers of data therebetween on said bus means without intervention by said central processing unit, at least one group of N+1 peripheral processors, each peripheral processor of said one group arranged to address a respective memory compartment within said memory means, the memory compartments being operatively connected to said bus means, said central processing system including means for detecting failure of one of said N+1 peripheral processors, a plurality of N controlled switchover modules, a respective switchover module corresponding to respective peripheral processors except peripheral processor N+1, said switchover modules being responsive to said means for detecting failure, a plurality of peripheral devices connected respectively via N switchover modules to N peripheral processors when said switchover modules are arranged in a first position, said peripheral processor N+1 not being connected to one of said plurality of peripheral devices when said switchover modules are in said first position, and said N+1 peripheral processor being connected to the peripheral devices connected to a preselected one of said switchover modules when the preselected switchover module is arranged in a second position. - View Dependent Claims (25)
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26. An intermemory communication system for providing redundant communication and transfer of data between memories of at least two computer systems, each computer system having at least one central processing unit means for processing data in response to instructions and memory means for storing programs and data, the intermemory communication system comprising:
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a plurality of intermemory link means for interconnecting respective memories as part of respective said computer systems, each intermemory link including at least two cables, a plurality of link adaptors for interfacing respective memory means of each of said computer systems, each link adaptor having a pair of tapping means for coupling to one of said intermemory links, one respective tap coupled to one cable of a respective intermemory link, each link adaptor including a receive buffer and a transmit buffer, said transmit buffer including means for indicating a busy status when data are presently stored therein and means for indicating a free status when data have been transferred to an intermemory link, and wherein each link adaptor has arbitrating control means effective to arbitrate the use of an intermemory link common to a plurality of link adaptors, and DMA interface controller means initiated by a central processing unit in a respective computer system for operatively connecting and transferring a number of data blocks via selected link adaptors and said intermemory link to a preselected computer system defined as a destination computer system without interfering with the central processing units of said respective computer system and said preselected computer system, said DMA interface controller means having means for transferring said number of data blocks to a selected free transmit buffer of a link adaptor operatively connected to the corresponding link adaptor of the destination computer system via a first intermemory link adaptor and being effective to repetitively select another free transmit buffer of a link adaptor being operatively connected to said destination computer system via a different intermemory link until a confirming message has been received from the DMA interface controller means of the destination computer system indicating that the number of data blocks is received valid within a predetermined time period after the transfer of the data blocks to a selected transmit buffer. - View Dependent Claims (27, 28, 29, 30)
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Specification