Watchdog timer
First Claim
1. A watchdog timer comprising;
- a register (2) for presetting predetermined DATA upon receipt of a writing signal (WT),a counter (4) which is incremented by a clock pulse (φ
),a comparator (3) which compares contents of said register (2) with contents of said counter and providing a coincidence output signal when two contents coincide with each other,a first flip-flop (F1) for storing said coincidence output signal for one period of said clock pulse φ
,a second flip-flop (F2) for storing said coincidence output signal upon receipt of said clock pulse φ
,a third flip-flop (F3) for storing output of said second flip-flop F2 upon receipt of said clock pulse φ
,an AND circuit (G1) for providing logical product of a reverse output Q1 of said first flip-flop F1 and said writing signal(WT) , andan OR circuit (G2) for receiving an output of said third flip-flop F3 and an output of said AND circuit (G1) and producing an alarm signal NG which indicates an error of a computer to be monitored.
1 Assignment
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Accused Products
Abstract
A watchdog timer for monitoring the operation of a computer monitors if the period of a writing signal (WT) generated by each execution of an instruction of a program is within the predetermined duration. The present watchdog timer comprises a register (2) for storing predetermined DATA upon receipt of the writing signal (WT), a counter (4) which is incremented by a clock pulse (φ), a comparator (3) for providing coincidence output signal when content of the counter reaches said predetermined DATA in the register (2), a first flip-flop (F1) for storing said coincidence output signal for one period of said clock pulse (φ), a second flip-flop (F2) for storing said coincidence output signal upon receipt of said clock pulse (φ), a third flip-flop (F3) for storing output of said second flip-flop (F2) upon receipt of said clock pulse (φ), an AND circuit (G1) for providing logical product of reverse output (Q1) of said first flip-flop (F1) and said writing signal (WT), and an OR circuit (G.sub. 2) for receiving an output of said third flip-flop (F3) and an output of said AND circuit (G1) and producing an alarm signal NG which indicates an error of a computer to be monitored.
42 Citations
4 Claims
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1. A watchdog timer comprising;
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a register (2) for presetting predetermined DATA upon receipt of a writing signal (WT), a counter (4) which is incremented by a clock pulse (φ
),a comparator (3) which compares contents of said register (2) with contents of said counter and providing a coincidence output signal when two contents coincide with each other, a first flip-flop (F1) for storing said coincidence output signal for one period of said clock pulse φ
,a second flip-flop (F2) for storing said coincidence output signal upon receipt of said clock pulse φ
,a third flip-flop (F3) for storing output of said second flip-flop F2 upon receipt of said clock pulse φ
,an AND circuit (G1) for providing logical product of a reverse output Q1 of said first flip-flop F1 and said writing signal(WT) , and an OR circuit (G2) for receiving an output of said third flip-flop F3 and an output of said AND circuit (G1) and producing an alarm signal NG which indicates an error of a computer to be monitored. - View Dependent Claims (2, 3, 4)
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Specification