3-Wire multiplexer

• US 4,569,045 A
• Filed: 06/06/1983
• Issued: 02/04/1986
• Est. Priority Date: 06/06/1983
• Status: Expired due to Fees

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Schieble, David L., Rutchik, Walter L., Swinehart, Merle R.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US06/501,661
• Time in Patent Office: 974 Days
• Field of Search: 370/85, 370/100, 370/110.1, 370/88, 370/97, 179/170 J, 340/310 R, 340/310 A
• US Class Current: 370/527
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5425 improving S/N by matching impedance, noise reduction, gain control
• CPC Class Codes: H04B 2203/5458 Monitor sensor; Alarm systems
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 2203/5495 having measurements and testing channel
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04J 7/02 in which the polarity of the amplitude is characteristic
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

The invention provides a 3-wire multiplexing system exhibiting high noise immunity, particularly suitable for industrial control applications. A master station provides AC power, and clocking and synchronization information, for a plurality of remote transmitter and receiver stations. A 3-wire cable links the master station and the remote stations. Two wires of the cable are power lines L1 and L2 and are isolated from each station by respective transformers. The third wire is a data line and is optically coupled to the remote stations. The remote stations are thus completely isolated from the cable, yet powered, clocked and synchronized therefrom without the need for local power supplies or local clocks. The signaling method switches the data line onto the power lines, and provides a high degree of data security by recognizing both the polarity and the position of a pulse on the data line within an AC cycle. The system further provides diagnostics in remote receivers including half cycle polarity and position decoding, error detection, fail state selection to fail OFF or fail ON or remain in the last valid state, and two scans alike detection.

Claims

1. A high noise immunity multiplexing system comprising:

a master station;

a plurality of remote stations; and

a cable comprising three shielded wires linking said master station and said remote stations, two wires of said cable being power lines L1 and L2 for powering and for clocking said remote stations from said master station, such that said remote stations do not require local power supplies and do not require local clocks, a third wire of said cable being a data line, and further comprising a signaling system for carrying data comprising switching said data line into connection with said power lines in accordance with a given signaling format;

wherein said power lines carry AC power, and said signaling system comprises switching one of said AC power lines into connection with said data line at designated times;

wherein said signaling system uses one or more AC cycles per multiplex channel and provides data security by recognizing the polarity or the position, or both, of a pulse on said data line relative to an AC cycle.

2. The invention according to claim 1 wherein said signaling system uses a single AC cycle per multiplex channel and provides data security by recognizing both the polarity and the position within a cycle of a pulse on said data line.

3. A high noise immunity multiplexing system comprising:

a master station;

a plurality of remote stations; and

a cable comprising three shielded wires linking said master station and said remote stations, two wires of said cable being power lines L1 and L2 for powering and for clocking said remote stations from said master station, such that said remote stations do not require local power supplies and do not require local clocks, a third wire of said cable being a data line, and further comprising a signaling system for carrying data comprising switching said data line into connection with said power lines in accordance with a given signaling format;

wherein said power lines carry AC power, and said signaling system comprises switching one of said AC power lines into connection with said data line at designated times;

wherein;

one logic state is encoded by closing a switch between said data line and one of said AC power lines during a positive half cycle of the AC waveform, and opening the switch during a negative half cycle of the AC waveform; and

the opposite logic state is encoded by opening the switch during a positive half cycle of the AC waveform, and closing the switch during a negative half cycle of the AC waveform.

4. A high noise immunity multiplexing system comprising:

a master station;

a plurality of remote stations; and

a cable comprising three shielded wires linking said master station and said remote stations, two wires of said cable being power lines L1 and L2 for powering and for clocking said remote stations from said master station, such that said remote stations do not require local power supplies and do not require local clocks, a third wire of said cable being a data line, and further comprising a signaling system for carrying data comprising switching said data line into connection with said power lines in accordance with a given signaling format;

wherein said power lines carry AC power, and said signaling system comprises switching one of said AC power lines into connection with said data line at designated times;

wherein said master station and said remote stations are each linked to said cable through respective transformer means to provide isolation from said cable such that each said remote station may have its own reference potential independently of other remote stations and do not interfere with system operation.

5. The invention according to claim 4 further comprising isolation means comprising a plurality of switch means, one for each said remote station, for switching said data line into connection with said power lines or for reading said data line, each said switch means being optically triggered by addressed channel responsive means at its respective remote station, whereby to provide full isolation of said remote stations from said cable.

6. The invention according to claim 5 wherein said AC power lines also carry system synchronization information, and wherein AC power, clock and synchronization information all are transformer coupled, data being optically coupled, and there being no ohmic connection between said cable and said remote stations.

7. A high noise immunity multiplexing system comprising:

a master station;

a plurality of remote stations;

a cable comprising three shielded wires linking said master station and said remote stations, two wires of said cable being power lines L1 and L2 for powering and for clocking said remote stations from said master station, such that said remote stations do not require local power supplies and do not require local clocks, a third wire of said cable being a data line, wherein said power lines carry AC power; and

a signaling system for switching said data line into connection with said power lines for carrying signal data using one or more AC cycles per multiplex channel, and wherein said master station includes means for periodically skipping one or more cycles on said AC power lines at given intervals to set scan length and synchronize said remote stations.

8. A high noise immunity multiplexing system comprising:

a master station for generating power, clocking and synchronization signals;

a cable comprising three shielded wires, two of which are power lines linked to said master station, the third wire being a data line;

at least one remote transmitter station linked to said cable and including means synchronized by said synchronization signal and clocked by said clocking signal for connecting one of said power lines to said data line at a given addressed channel; and

at least one remote receiver station linked to said cable and including means synchronized by said synchronization signal and clocked by said clocking signal for reading the state of said data line at a given addressed channel,

wherein;

said master station is linked to said power lines by transformer coupling means;

said remote transmitter station is linked to said power lines by transformer coupling means;

said remote transmitter station is linked to said data line by optical coupling means;

said remote receiver station is linked to said power line by transformer coupling means; and

said remote receiver station is linked to said data line by optical coupling means.

9. The invention according to claim 8 wherein said master station generates an AC waveform which provides power and clocking for said remote stations such that the latter do not require local power supplies or local clocks, and including means for skipping one or more AC cycles at given intervals to synchronize said remote stations and set scan length.

10. The invention according to claim 9 wherein said remote transmitter means includes transmit logic encoding means for connecting one of said power lines to said data line at a given address channel during one or the other of designated periods of said AC waveform according to the data state of a sensor at said remote transmitter station.

11. The invention according to claim 10 wherein said remote transmitter means includes transmit logic encoding means for connecting one of said power lines to said data line during one or the other of designated half cycles of said AC waveform according to the data state of a sensor at said remote transmitter station.

12. The invention according to claim 10 wherein said remote receiver means includes cycle detect and receive enable logic means for reading said data line.

13. The invention according to claim 12 wherein said remote receiver means reads said data line during designated periods of the AC waveform, and including decode logic means for sampling the states of said data line.

14. The invention according to claim 13 wherein said remote receiver means reads said data line during designated first and second half cycles during the AC waveform, and including decode logic means for sampling the positive and negative states of said data line.

15. The invention according to claim 13 wherein the signaling system uses a single AC cycle per multiplex channel and provides data security by recognizing both the polarity and the position of a pulse on said data line within an AC cycle, one logic state being a positive half cycle in sequence with a null half cycle, and the opposite logic state being a null half cycle in sequence with a negative half cycle.

16. The invention according to claim 15 wherein said remote receiver means includes said cycle detect and receive enable logic means for reading said data line at a discrete point during the first half cycle and again at a discrete point during the second half cycle of said AC waveform, and including said decode logic means for sampling the positive and negative states of said data line during each half cycle.

17. A high noise immunity multiplexing system comprising:

(a) a master station outputting an AC waveform providing power and clocking, and periodically skipping one or more AC cycles at given intervals to set scan length and provide synchronization;

(b) a cable comprising three shielded wires, two of which are power lines transformer-coupled to said master station, the third wire being a data line;

(c) at least one remote transmitter station transformer-coupled to said power lines and comprising;

(i) sync detect means responsive to said AC waveform from said last mentioned transformer for detecting said skipped AC cycle;

(ii) address counter means responsive to said sync detect means and clocked by said AC waveform from said last mentioned transformer for generating an address valid output signal at a given addressed channel;

(iii) a sensor data latch responsive to said address valid signal for outputting sensor data;

(iv) transmit logic means responsive to said AC clocking waveform from said last mentioned transformer, and responsive to said address valid signal, and responsive to said sensor data latch, for emitting an optical actuation signal; and

(v) transmit switch means responsive to said optical actuation signal for connecting one of said power lines to said data line; and

(d) at least one remote receiver station transformer-coupled to said power lines and comprising;

(i) sync detect means responsive to said AC waveform from said last mentioned transformer for detecting said skipped AC cycle;

(ii) address counter means responsive to said last mentioned sync detect means and clocked by said AC waveform from said last mentioned transformer for generating an address valid output signal at a given addressed channel;

(iii) receive switch means for reading said data line, and including light emitting means emitting an optic signal in response to current flow on said data line; and

(iv) decode logic means responsive to said optic signal for outputting the decoded logic state of said data line during said addressed channel.

18. The invention according to claim 17 wherein said remote receiver station further comprises receive enable logic means responsive to said address valid signal for emitting an optical actuation signal, said optical actuation signal disconnecting said receive switch means from the data line except at a given address channel.

19. The invention according to claim 17 wherein said remote receiver station comprises:

cycle detect means responsive to said AC waveform from said last mentioned transformer for outputting triggering signals;

receive enable logic means responsive to said triggering signals from said cycle detect means and responsive to said address valid signal, for emitting an optical actuation signal;

said receive switch means being responsive to said last mentioned optical actuation signal for reading said data line, and including first light emitting means emitting a plus sense optic signal in response to one direction of current flow on said data line, and including second light emitting means emitting a minus sense optic signal in response to the opposite direction current flow on said data line; and

said decode logic means being responsive to said plus and minus sense optic signals for outputting the decoded logic state of said data line during said addressed channel.

20. The invention according to claim 19 wherein said remote receiver station cycle detect means responsive to said AC waveform outputs said triggering signal during each half cycle of said AC waveform.

21. The invention according to claim 20 comprising:

a signaling system using a single AC cycle per multiplex channel and providing data security by recognizing both the polarity and the position of a pulse on said data line within an AC cycle, said transmit logic means encoding one logic state on said data line by closing said transmit switch means during the positive half cycle of said AC waveform and opening said transmit switch means during the negative half cycle of said AC waveform, said transmit logic means encoding the opposite logic state on said data line by opening said transmit switch means during the positive half cycle of said AC waveform and closing said transmit switch means during the negative half cycle of said AC waveform;

said receive enable logic means closing said receive switch means during each of the first and second half cycles of said AC waveform during the addressed channel to sample the state of said data line during each half cycle;

and further comprising error detect means in said remote receiver means responsive to said decode logic means and outputting an error signal in response to an invalid combination of polarity and position of said plus and minus sense signals.

22. The invention according to claim 17 comprising:

a signaling system using a single AC cycle per multiplex channel and providing data security by recognizing both the polarity and the position of a pulse on said data line within an AC cycle, said transmit logic means encoding one logic state on said data line by closing said transmit switch means during the positive half cycle of said AC waveform and opening said transmit switch means during the negative half cycle of said AC waveform, said transmit logic means encoding the opposite logic state on said data line by opening said transmit switch means during the positive half cycle of said AC waveform and closing said transmit switch means during the negative half cycle of said AC waveform, said receive switch means including first light emitting means emitting a plus sense optic signal in responsive to one direction of current flow on said data line, and including second light emitting means emitting a minus sense optic signal in response to the opposite direction current flow on said data line;

said receiver further comprising cycle detect means responsive to said AC waveform for outputting trigger signals during each of the first and second half cycles of said AC waveform during the addressed channel to sample the state of said optic signal during each half cycle;

and further comprising error detect means in said remote receiver means responsive to said decode logic means and outputting an error signal in response to an invalid combination of polarity and position of said decoded logic state.

23. The invention according to claim 22 further comprising fail state select logic means in said remote receiver means and responsive to an error signal from said error detect logic means for outputting a data state according to a user preselected option of fail ON, fail OFF, or remain in last state, such that when an error is detected, the output of said fail state select logic will be a user selected LOGIC 1, or LOGIC 0, or will remain in the last valid data state.

24. The invention according to claim 23 wherein:

said decode logic means comprises four flip-flops clocked by the output of said cycle detect means, a first flip-flop responsive to said plus sense signal, a second flip-flop responsive to the output of said first flip-flop, a third flip-flop responsive to said minus sense signal, and a fourth flip-flop responsive to the output of said third flip-flop, the output of one of said flip-flops at the end of a full AC cycle channel being the logic state of said data line;

said error detect logic comprises first OR means responsive to a given logic state output of either of two of said flip-flops to output an error signal, a comparator for comparing the output states of the remaining two flip-flops for outputting an error signal in response to a given relation therebetween, and second OR means responsive to either said first OR means or said comparator means for outputting an error signal;

said fail state select logic means includes user selectable switch means for selecting remain in last state or fail OFF or fail ON, said remain in last state mode tying an input of a first AND gate to a given state to disable the latter and prevent clocking of an output data latch, said fail OFF mode tying the input of a second AND gate to a given state to disable the latter, said error signal disabling a third AND gate, said second and third AND gates being input to an OR gate such that the output of the latter is in an OFF condition when the inputs from said second and third AND gates are disabled, said fail ON mode tying said input of said second AND gate to the opposite state to enable the latter to pass said error signal therethrough to said output OR gate such that the latter is in the ON condition.

25. The invention according to claim 17 further comprising two scans alike logic in said remote receiver station for comparing each scan data state of the addressed channel against the immediately preceeding scan data state, and updating data output only when the two states are the same, to prevent transient glitches from changing the data output state.

26. The invention according to claim 25 wherein:

said two scans alike logic comprises a flip-flop having an input from said decoded logic state, and including means for comparing the input to the output of said last mentioned flip-flop and means responsive thereto to enable said sync signal to clock said output data latch to pass the output of said last mentioned flip-flop therethrough when current scan data for the addressed channel is the same as the data for the immediately preceeding scan, said last mentioned flip-flop being clocked by the inverse of the sync signal to store current scan data for the next scan comparison.

27. The invention according to claim 22 wherein:

said sync detect means comprises a retriggerable monostable multivibrator having a time constant longer than the cycle of said AC waveform;

said transmit logic means comprises exclusive NOR means for changing polarity of said clocking AC waveform from said remote transmitter transformer responsive to the output of said sensor data latch, and AND gate having inputs from said exclusive NOR gate and from said address valid output of said address counter means, a transistor driven into conduction by the output of said last mentioned AND gate to conduct current through a light emitting diode; and

said transmit switch means comprises a phototransistor optically coupled to said light emitting diode and biased into conduction by the light emitted therefrom, and connected in a rectifying bridge circuit between said power line and said data line to conduct current therebetween in a direction according to the half cycle of conduction.

28. The invention according to claim 22 wherein:

said cycle detect means comprises a one-shot multivibrator pulser responsive to the clocking AC waveform from said receiver transformer and outputting one-shot pulses at each transition of said clocking AC waveform, and a monostable multivibrator responsive to said oneshot pulses for outputting a triggering waveform of twice the frequency of said AC clocking waveform and having a triggering pulse of given polarity transition occurring during each half cycle of said AC clocking waveform;

said sync detect means comprises retriggerable monostable multivibrator means having a time constant greater than one cycle of said AC clocking waveform;

said receive switch means comprises a rectifying bridge connected to said data line, a first light emitting diode in one branch of said bridge for emitting light when current flows in one direction on said data line, and a second light emitting diode in the other branch of said bridge for emitting light when current flows in the opposite direction on said data line, and

further comprising first phototransistor means responsive to said first light emitting diode outputting a plus sense signal, and second phototransistor means responsive to said second light emitting diode outputting a minus sense signal, said plus and minus sense signals being clocked into said decode logic means by said cycle detect triggering pulses.

29. The invention according to claim 21 further comprising fail state select logic means in said remote receiver means and responsive to an error signal from said error detect logic means for outputting a data state according to a user preselected option of fail ON, fail OFF, or remain in last state, such that when an error is detected, the output of said fail state select logic will be a user selected LOGIC 1, or LOGIC 0, or will remain in the last valid data state.

30. The invention according to claim 29 further comprising two scans alike logic in said remote receiver station and responsive to said fail state select logic for comparing each scan data state of the addressed channel against the immediately preceeding scan data state, and updating data only when the two states are the same, to prevent transient glitches from changing the data output state.

31. The invention according to claim 30 wherein:

said decode logic means comprises a shift register including four flip-flops clocked by the output of said cycle detect means through said receive enable logic means, a first flip-flop responsive to said plus sense signal, a second flip-flop responsive to the output of said first flip-flop, a third flip-flop responsive to said minus sense signal, and a fourth flip-flop responsive to the output of said third flip-flop, the output of one of said flip-flops at the end of a full AC cycle channel being the logic state of said data line;

said error detect logic comprises first OR means responsive to a given logic state output of either of two of said flip-flops to output an error signal, a comparator for comparing the output states of the remaining two flip-flops for outputting an error signal in response to a given relation therebetween, and second OR means responsive to either said first OR means or said comparator means for outputting an error signal;

said fail state select logic means includes user selectable switch means for selecting remain in last state or fail OFF or fail ON, said remain in last state mode tying an input of a first AND gate to a given state to disable the latter and prevent clocking of an output data latch, said fail OFF mode tying the input of a second AND gate to a given state to disable the latter, said error signal disabling a third AND gate, said second and third AND gates being input to an OR gate such that the output of the latter is in an OFF condition when the inputs from said second and third AND gates are disabled, said fail ON mode tying said input of said second AND gate to the opposite state to enable the latter to pass said error signal therethrough to said output OR gate such that the latter is in the ON condition; and

said two scans alike logic comprises a flip-flop clocked by the inverse of the sync signal from said sync detect means to said address counter means, said flip-flop having an input from said output OR gate of said fail state select logic, and including means for comparing the input to the output of said last mentioncd flip-flop and means responsive thereto to enable said sync signal to clock said output data latch to pass the output of said last mentioned flip-flop therethrough when current scan data for the addressed channel is the same as the data for the immediately preceeding scan.

32. The invention according to claim 19 wherein:

said sync detect means comprises a retriggerable monostable multivibrator having a time constant longer than the cycle of said AC waveform;

said transmit logic means comprises exclusive NOR means for comparing said clocking AC waveform from said remote transmitter transformer and the output of said sensor data latch, an AND gate having inputs from said exclusive NOR gate and from said address valid output of said address counter means, a transistor driven into conduction by the output of said last mentioned AND gate to conduct current through a light emitting diode; and

said transmit switch means comprises a phototransistor optically coupled to said light emitting diode and biased into conduction by the light emitted therefrom, and connected in a rectifying bridge circuit between said power line and said data line to conduct current therebetween in a direction according to the half cycle of conduction.

33. The invention according to claim 19 wherein:

said cycle detect means comprises a one-shot multivibrator pulser responsive to the clocking AC waveform from said receiver transformer and outputting one-shot pulses at each transition of said clocking AC waveform, and a monostable multivibrator responsive to said one-shot pulses for outputting a triggering waveform of twice the frequency of said AC clocking waveform and having a triggering pulse of given polarity transition occuring during each half cycle of said AC clocking waveform;

said sync detect means comprises retriggerable monostable multivibrator means having a time constant greater than one cycle of said AC clocking waveform;

said receive enable logic means having its input from said address valid output of said address counter means, and transistor means biased into conduction by the output of said AND gate for conducting current through a light emitting diode once during each half cycle of said AC waveform according to said triggering pulse waveform; and

said receive switch means comprises a phototransistor optically coupled to said light emitting diode and responsive to light emitted therefrom to conduct current through a rectifying bridge connected to said data line, a second light emitting diode in one branch of said bridge for emitting light when current flows in one direction on said data line, and a third light emitting diode in the other branch of said bridge for emitting light when current flows in the opposite direction on said data line.