Multiple frequency digital phase locked loop

• US 4,574,243 A
• Filed: 01/03/1984
• Issued: 03/04/1986
• Est. Priority Date: 01/03/1984
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Levine, Stephen N.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Callahan, Timothy P.
• Application Number:
  US06/567,715
• Time in Patent Office: 791 Days
• Field of Search: 328/15, 328/24, 328/25, 328/134, 328/155, 307/510, 307/511, 307/262, 307/271, 375/118, 375/119, 375/120, 331/1 A, 331/25
• US Class Current: 327/159
• CPC Class Codes: H03K 23/662 by adding or suppressing pulses
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

An improved multiple frequency digital phase-locked loop circuit is described. The improved digital phase-locked loops utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.

Claims

1. An improved multiple frequency digital phase locked loop (DPLL) for processing received data signal and producing an output signal which is phase-locked to the received data signal, comprising:

(a) phase comparator means having first and second inputs, wherein the first input is coupled to the received data signal and the second input is coupled to the DPLL output signal, and an output for providing an output signal indicative of the relative phase between said incoming data signal and said DPLL output signal;

(b) clock means for generating a reference clock signal;

(c) programmable divider means, coupled to said reference clock signal and having an output and programmable inputs, for generating a programmable clock signal related to said reference clock signal according to a divider ratio controlled by said programmable inputs;

(d) digital means, coupled to the output of said programmable divider means for generating first and second derived clock signals, one such signal being in a delayed relation to the other;

(e) phase and frequency adjust means coupled to said clock means for producing a composite clock signal by selectively adding or subtracting said first and second derived clock signals, periodically, at a rate defined by said programmable clock signal to effect a frequency adjustment or by individually adding or subtracting pulses in response to said phase comparator output signal to effect a phase adjustment;

(f) frequency divider means coupled to said phase and frequency adjust means for processing said composite clock signal to produce the digital phase-locked loop output signal.

2. The multiple frequency DPLL as defined in claim 1 further including bandwidth control means coupled between said phase comparator means and said phase and frequency adjust means, having a plurality of programmable inputs which indicate a desired operating bandwidth for the multiple frequency DPLL, said bandwidth control means producing an output signal, which effects phase adjustments in variable increments by causing phase corrections to be made by adding or subtracting groups of pulses from said composite clock signal as determined by said programmable inputs.