Fourier transform processor

• US 4,581,715 A
• Filed: 09/28/1982
• Issued: 04/08/1986
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/425,731
• Time in Patent Office: 1,288 Days
• Field of Search: 364/724, 364/725, 364/726, 364/728
• US Class Current: 708/403
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An improved Fourier transform processor is provided for generating frequency domain output signals in response to time domain input signals. Various configurations are provided. Processing on the fly as samples are received yields improvements such as greater speed and reduced circuitry. Generating higher resolution output samples in response to lower resolution input samples yields improvements such greater precision and reduced circuitry. Directly combining complex signal components yields improvements such as greater SNR and reduced circuitry. Single bit processing yields improvements such as greater speed and reduced circuitry.

Claims

1. A Fourier transform processor comprising:

incremental input means for generating incremental input signal samples;

Fourier transform reference means for generating Fourier transform reference signal samples;

Fourier transform product means for generating Fourier transform product signal samples by multiplying the incremental input signal samples generated with said incremental input means and the Fourier transform reference signal samples generated with said Fourier transform reference means; and

Fourier transform summing means for generating Fourier transformed output signal samples by adding the Fourier transform product signal samples.

2. The Fourier transform processor as set forth in claim 1 above, wherein said Fourier transform reference means includes incremental Fourier transform reference means for generating the Fourier transform reference signal samples as incremental Fourier transform reference signal samples;

wherein said Fourier transform product means includes incremental Fourier transform product means for generating the Fourier transform product signal samples as incremental Fourier transform product signal samples by multiplying the incremental input signal samples generated with said incremental input means and the incremental Fourier transform reference signal samples generated with said incremental Fourier transform reference means; and

wherein said Fourier transform summing means includes incremental Fourier transform summing means for generating the Fourier transformed output signal samples as multiple bit digital Fourier transformed output signal samples by adding the incremental Fourier transform product signal samples.

3. The Fourier transform processor as set forth in claim 1 above, wherein said incremental input means is implemented with a charge coupled device for generating the incremental input signal samples in response to a geophysical exploration-related input seismic signal, wherein said Fourier transform reference means is implemented with an analog charge coupled device for generating the Fourier transform reference signal samples in analog signal form, wherein said Fourier transform product means is implemented with an analog charge coupled device for generating the Fourier transform product signal samples as analog Fourier transform product signal samples by multiplying the incremental input signal samples generated with said charge coupled device incremental input means and the analog Fourier transform reference signal samples generated with said analog charge coupled device Fourier transform reference means, wherein said Fourier transform summing means is implemented with a charge coupled device for generating the Fourier transformed output signal samples as analog Fourier transformed output signal samples by adding the analog Fourier transform product signal samples, and wherein said processor further includes means for generating underground structure-related digital Fourier transformed output signal samples.

4. A Fourier transform processor comprising:

input means for generating incremental input signal samples;

reference means for generating Fourier transform reference signal samples;

product means for generating Fourier product signal samples by multiplying the incremental input signal samples generated with said input means by the Fourier transform reference signal samples generated with said reference means; and

summing means for generating Fourier transformed signal samples by summing the product signal samples generated with said product means.

5. A Fourier transform processor comprising:

incremental input means for generating incremental digital input signal samples;

incremental reference means for generating incremental digital Fourier reference signal samples;

incremental product means for generating incremental digital Fourier product signal samples by multiplication of the incremental digital input signal samples generated with said incremental input means and the incremental digital Fourier reference signal samples generated with said incremental reference means; and

incremental adding means for generating digital Fourier transformed signal samples each having a plurality of digital bits by incrementally adding the incremental digital Fourier product signal samples generated with said incremental product means.

6. A filtering system comprising:

first signature means for generating a first signature signal having a first signature;

first communication means for communicating the first signature signal generated with said first signature means;

second signature means for generating a second signature signal having a second signature that is seperable from said first signature;

second communication means for communicating the second signature signal generated with said second signature means;

combining means for generating a combined signature signal by combining the first signature signal communicated with said first communication means and the second signature signal communicated with said second communication means;

seperating means for seperating the first signature signal and the second signature signal from the combined signature signal generated with said combining means, said seperating means including

(a) first reference means for generating a first signature reference signal having a signature the same as the first signature associated with the first signature signal generated with said first signature means,

(b) a first correlation processor for generating a firs correlation output signal by correlating the combined signature signal generated with said combining means and the first signature reference signal generated with said first reference means,

(c) second reference means for generating a second signature reference signal having a signature the same as the second signature associated with the second signature signal generated with said second signature means, and

(d) a second correlation processor for generating a second correlation output signal by correlating the combined signature signal generated with said combining means and the second signature reference signal generated with said second reference means;

first locating means for locating a first object in response to the first correlation output signal generated with said first correlation processor; and

second locating means for locating a second object in response to the second correlation output signal generated with said second correlation processor.

7. A Fourier transform processor comprising:

input means for generating input signal samples;

reference means for generating Fourier transform reference signal samples;

output means for storing Fourier transformed output signal samples;

product means for generating Fourier transformed product signal samples by multiplying a single input signal sample generated with said input means by a plurality of the Fourier transform reference signal samples generated with said reference means before multiplying another input signal sample generated with said input means by a Fourier transform reference signal sample generated with said reference means; and

update means for updating the Fourier transformed output signal samples stored in said output means by adding the Fourier transformed product signal samples generated with said product means and the Fourier transformed output signal samples stored in said output means.

8. A Fourier transform filter processor comprising:

input means for generating input signal samples;

reference means for generating Fourier transform reference signal samples;

product means for generating product signal samples by multiplying the input signal samples generated with said input means and the Fourier transform reference signal samples generated with said reference means;

an output memory for storing Fourier transformed output signal samples; and

summing means for progressively building up magnitude of the Fourier transformed output signal samples stored in said output memory by adding the product signal samples generated with said product means to the Fourier transformed output signal samples stored in said output memory.

9. A Fourier transform processor comprising:

input means for generating input signal samples;

Fourier transform reference means for generating Fourier transform reference signal samples;

Fourier transform output memory means for storing Fourier transformed output signal samples; and

Fourier transform update means for updating the Fourier transformed output signal samples stored in said Fourier transform output memory means in response to the input signal samples as they are generated with said input means, said Fourier transform update means including product means for generating a plurality of product signal samples by multiplying an input signal sample generated with said input means and a plurality of Fourier transform reference signal samples generated with said Fourier transform reference means and summing means for adding the product signal samples generated with said product means to the output signal samples stored in said Fourier transform output memory means.

10. A fast Fourier transform processor comprising:

input means for generating single bit resolution digital input signal samples;

reference means for generating fast Fourier transform reference signal samples;

product means for generating fast Fourier transform product signal samples by multiplying the single bit resolution digital input signal samples generated with said input means and the fast Fourier transform reference signal samples generated with said reference means; and

summing means for generating multiple bit digital fast Fourier transformed output signal samples by summing the fast Fourier transform product signal samples generated with said product means.

11. A Fourier processor comprising:

input means for generating input signal samples;

Fourier transform reference means for storing single bit resolution digital Fourier transform reference signal samples;

product means for generating Fourier transform product signal samples by multiplying the input signal samples generated with said input means and the single bit resolution digital Fourier transform reference signal samples stored in said Fourier transform reference means; and

summing means for generating Fourier transformed output signal samples by summing the Fourier transform product signal samples generated with said product means.

12. A Fourier transform processor comprising:

input means for generating lower resolution digital input signal samples;

reference means for generating digital reference signal samples;

product means for generating digital product signal samples by multiplying lower resolution digital input signal samples generated with said input means and digital reference signal samples generated with said reference means; and

summing means for generating higher resolution Fourier transformed digital signal samples having better digital resolution then said lower resolution digital input signal samples.

13. A filter system comprising:

a modulator for generating a combined signature signal to communicate signal samples, said modulator including

(a) first input means for generating a first input signal,

(b) second input means for generating a second input signal,

(c) first signature means for generating a first signature signal modulated with the first input signal generated with said first input means,

(d) second signature means for generating a second signature signal modulated with the second input signal generated with said second input means, and

(e) combining means for generation a combined signature signal by combining the first signature signal generated with said first signature means and the second signature signal generated with said second signature means;

communicating means for communicating the combined signature signal generated with said combining means to a demodulator located remote from said modulator; and

a demodulator for reconstructing the first input signal and the second input signal by demodulating the combined signature signal communicated with said communicating means, said demodulator including

(a) first reference means for generating a first reference signal having a signature related to the first signature of the first signature signal modulated by said first signature means,

(b) a first correlation processor for reconstructing the first input signal by correlating the combined signature signal communicated with said communicating means and the first reference signal generated with said first reference means,

(c) second reference means for generating a second reference signal having a signature related to the second signature of the second signature signal modulated by said second signature means,

(d) a second correlation processor for reconstructing the second input signal by correlating the combined signature signal communicated with said communicating means and the second reference signal generated with said second reference means,

(e) first output means for outputting the first input signal reconstructed by said first correlation processor, and

(f) second output means for outputting the second input signal reconstructed by said second correlation processor.

14. The system as set forth in claim 13 above, further comprising:

first locating means for locating a first object by processing the reconstructed first input signal output by said first output means and

second locating means for locating a second object by processing the reconstructed second input signal output by said second output means.

15. The system as set forth in claim 13 above, further comprising:

first timing means for determining a first time delay from a first object by processing the reconstructed first input signal output by said first output means and

second timing means for determining a second time delay from a second object by processing the reconstructed second input signal output by said second output means.

16. A filter system comprising:

a first modulator for generating a first signature signal to communicate first signal samples, said first modulator including

(a) first input means for generating a first input signal,

(b) first signature means for modulating a first signature signal with the first input signal generated with said first input means, and

(c) first communicating means for communicating the first signature signal modulated with said first signature means to a demodulator being located remote from said first modulator;

a second modulator for generating a second signature signal to communicate second signal samples, said second modulator including

(a) second input means for generating a second input signal,

(b) second signature means for modulating a second signature signal with the second input signal generated with said second input means, and

(c) second communicating means for communicating the second signature signal modulated with said second signature means to said demodulator being located remote from said second modulator; and

a demodulator for reconstructing the first input signal communicated with said first communicating means and for reconstructing the second input signal communicated with said second communicating means, said demodulator including

(a) a first correlation processor for reconstructing the first input signal by correlating the first signature signal communicated with said first communicating means with a first reference signal having a signature related to the first signature signal modulated by said first signature means,

(b) a second correlation processor for reconstructing the second input signal by correlating the second signature signal communicated with said second communicating means with a second reference signal having a signature related to the second signature signal modulated by said second signature means,

(c) first output means for outputting the first input signal reconstructed by said first correlation processor, and

(d) second output means for outputting the second input signal reconstructed by said second correlation processor.

17. The system as set forth in claim 16 above, further comprising:

first locating means for locating a first object by processing the reconstructed first input signal output by said first output means and

second locating means for locating a second object by processing the reconstructed second input signal output by said second output means.

18. The system as set forth in claim 16 above, further comprising:

first timing means for determining a first time delay from a first object by processing the reconstructed first input signal output by said first output means and

second timing means for determining a second time delay from a second object by processing the reconstructed second input signal output by said second output means.

19. A Fourier transform processor comprising:

input means for generating input signal samples;

reference means for storing Fourier transform reference signal samples;

memory means for storing Fourier transformed output signal samples; and

on the fly processing means for updating the Fourier transformed output signal samples stored in said memory means on the fly in response to the input signal.

20. A frequency domain transform processor comprising:

input means for generating input signal samples;

frequency domain transform reference means for storing frequency domain related reference signal samples;

an output memory for storing frequency domain output signal samples; and

update means for updating the frequency domain output signal samples stored in said output memory in response to each of the input signal samples as the input signal samples are generated with said input means, said update means including

(a) frequency domain product means for generating a plurality of frequency domain product signal samples by multiplying each of the input signal samples generated with said input means and a plurality of frequency domain related reference signal samples stored with said frequency domain transform reference means and

(b) summing means for adding the frequency domain product signal samples generated with said frequency domain product means to the frequency domain output signal samples stored in said output memory means.

21. The processor as set forth in claim 20 above, wherein said frequency domain transform reference means includes means for storing the frequency domain related reference signal samples as single bit resolution digital frequency domain related reference signal samples;

wherein said frequency domain product means includes means for generating the plurality of frequency domain product signal samples by multiplying each of the input signal samples generated with said input means and a plurality of the single bit resolution digital frequency domain related reference signal samples generated with said frequency domain transform reference means; and

wherein said summing means includes means for adding the frequency domain product signal samples generated with said frequency domain product means to the frequency domain output signal samples stored in said output memory means to generate the frequency domain output signal samples stored in said output memory means as multiple bit frequency domain output signal samples.

22. A frequency domain transform processor comprising:

input means for generating single bit resolution input signal samples;

frequency domain transform reference means for generating frequency domain related reference signal samples;

an output memory for storing frequency domain output signal samples; and

update means for updating the frequency domain output signal samples stored in said output memory in response to the single bit resolution input signal samples generated with said input means, said update means including

(a) frequency domain product means for generating a plurality of frequency domain product signal samples by multiplying each of the single bit resolution input signal samples generated with said input means and a plurality of frequency domain related reference signal samples generated with said frequency domain transform reference means and

(b) summing means for adding the frequency domain product signal samples generated with said frequency domain product means to the frequency domain output signal samples stored in said output memory means.

23. A fast Fourier transform processor system comprising:

input means for generating lower resolution input signal samples;

fast Fourier transform reference means for generating fast Fourier transform reference signal samples;

fast Fourier transform product means for generating fast Fourier transform product signal samples by multiplying the lower resolution input signal samples and the fast Fourier transform reference signal samples; and

summing means for generating higher resolution fast Fourier transformed output signal samples having higher digital resolution than said input signal samples by summing the fast Fourier transform product signal samples generated with said fast Fourier transform product means.

24. A filter system comprising:

a plurality of input signature signal generators each arranged for generating an input signature signal having a signature different from the signatures of the other input signature signals generated with the other input signature signal generators in said plurality of input signature signal generators and having a signature seperable from the signatures of the other input signature signals generated with the other input signature signal generators in said plurality of input signature signal generators;

combining means for generating a combined signature signal by combining the plurality of input signature signals generated with said plurality of input signature signal generators; and

a plurality of correlation processors each arranged for generating a correlation output signal by correlating the combined signature signal generated with said combining means with a reference signature signal having a signature different from the signatures of the other reference signature signals in said plurality of correlation processors, having a signature seperable from the signatures of the other reference signature signals in said plurality of correlation processors, and having a signature the same as the signature of one of the input signature signals generated with said plurality of input signature signal generators.

25. A filter system comprising:

a modulator for generating a combined signature signal, said modulator including

(a) first signature means for generating a first signature signal having a first signature,

(b) second signature means for generating a second signature signal having a second signature that is different from said first signature, and

(c) combining means for generation a combined signature signal by combining the first signature signal generated with said first signature means and the second signature signal generated with said second signature means;

communicating means for communicating the combined signature signal generated with said combining means to a demodulator located remote from said modulator; and

a demodulator for demodulating the combined signature signal communicated with said communicating means, said demodulator including

(a) first reference means for generating a first reference signal having a signature related to the first signature of the first signature signal generated with said first signature means,

(b) a first correlation processor for generating a first output signal by correlating the combined signature signal communicated with said communicating means and the first reference signal generated with said first reference means,

(c) second reference means for generating a second reference signal having a signature related to the second signature of the second signature signal generated with said second signature means, and

(d) a second correlation processor for generating a second output signal by correlating the combined signature signal communicated with said communicating means and the second reference signal generated with said second reference means.

26. The system as set forth in claim 25 above, further comprising:

first locating means for locating a first object by processing the first output signal generated by said first correlation processor and

second locating means for locating a second object by processing the second output signal generated by said second correlation processor.

27. The system as set forth in claim 25 above, further comprising:

first timing means for determining a first time delay from a first object by processing the first output signal generated by said first correlation processor and

second timing means for determining a second time delay from a second object by processing the second output signal generated by said second correlation processor.

28. A filter system comprising:

first signature generating means for generating a first signature input signal having a first signature;

second signature generating means for generating a second signature input signal having a second signature that is different from the first signature of said first signature signal generated with said first signature means;

combining means for generating a combination signature signal by combining the first signature input signal generated with said first signature generating means and the second signature input signal generated with said second signature generating means;

first signature reference means for generating a first signature reference signal having a signature that is the same as the first signature of the first signature input signal generated with said first signature generating means;

second signature reference means for generating a second signature reference signal having a signature that is the same as the second signature of the second signature input signal generated with said second signature generating means;

a first correlator for generating a first correlated output signal by correlating the combination signature signal generated with said combining means and the first signature reference signal generated with said first signature reference means; and

a second correlator for generating a second correlated output signal by correlating the combination signature signal generated with said combining means and the second signature reference signal generated with said second signature reference means.

29. The system as set forth in claim 28 above, further comprising:

first locating means for locating a first object by processing the first correlated output signal generated by said first correlator and

second locating means for locating a second object by processing the second correlated output signal generated by said second correlator.

30. The system as set forth in claim 28 above, further comprising:

first timing means for determining a first time delay from a first object by processing the first correlated output signal generated by said first correlator and

second timing means for determining a second time delay from a second object by processing the second correlated output signal generated by said second correlator.

31. A Fourier transform processor comprising:

a charge coupled device for generating incremental input signal samples;

Fourier transform reference means for generation Fourier transform reference signal samples;

product means for generating Fourier transform product signal samples by multiplying the incremental input signal samples generated with said charge coupled device and the Fourier transform reference signal samples generated with said Fourier transform reference means; and

summing means for generating Fourier transformed output signal samples by summing the Fourier transform product signal samples generated with said product means.

32. A fast Fourier transform processor comprising:

input means for generating single bit resolution digital input signal samples;

fast Fourier transform reference means for generating multiple bit resolution digital fast Fourier transform reference signal samples;

product means for generating incremental digital fast Fourier transform product signal samples by multiplying the single bit resolution digital input signal samples generated with said input means and the multiple bit resolution digital fast Fourier transform reference signal samples generated with said fast Fourier transform reference means; and

summing means for generating multiple bit digital fast Fourier transformed output signal samples by summing the incremental digital fast Fourier transform product signal samples generated with said product means.

33. A Fourier processor comprising:

single bit input means for generating single bit input signal samples;

single bit Fourier transform reference means for generating single bit Fourier transform reference signals;

single bit product means for generating single bit Fourier transform product signals by multiplying the single bit input signal samples generated with said single bit input means and the single bit Fourier transform reference signals generated with said single bit Fourier transform reference means; and

summing means for generating multiple bit digital resolution Fourier transformed output signal samples by summing the single bit Fourier transform product signals generated with said single bit product means.

34. A filtering system comprising:

a plurality of signature signal generators for generating a plurality of signature signals each having a signature separable from the signatures of the other signature signals;

combining means for generating a combined signature signal by combining the plurality of signature signals together; and

correlation output means for generating a plurality of correlated output signals, said correlation output means including a plurality of correlation processors each generating one of the plurality of correlated output signals by correlating the combined signature signal with a reference signature signal, where the reference signature signal of each one of the plurality of correlation processors has a different one of the signature signal generator signatures that are separable from the signatures of the other signature signal generator signatures.

35. The system as set forth in claim 34 above, further comprising locating means for locating a plurality of objects by processing the plurality of correlated output signals generated by said plurality of correlation processors.

36. The system as set forth in claim 34 above, further comprising timing means for determining a plurality of time delays from a plurality of objects by processing the plurality of correlated output signals generated by said plurality of correlation processors.

37. A filter system comprising:

a first modulator for generating a first signature signal, said first modulator including

(a) first signature means for generating a first signature signal having a first signature and

(b) first communicating means for communicating the first signature signal generated with said first signature means to a demodulator;

a second modulator being located remote from said first modulator for generating a second signature signal, said second modulator including

(a) second signature means for generating a second signature signal having a second signature that is different from the first signature and

(b) second communicating means for communicating the second signature signal generated with said second signature means to said demodulator;

combining means for generating a combination signature signal by combining the first signature signal communicated with said first communicating means and the second signature signal communicated with said second communicating means; and

a demodulator being located remote from said first modulator and being located remote from said second modulator for processing the combination signature signal generated with said combining means to separate the first signature signal communicated with said first communicating means and the second signature signal communicated with said second communicating means, said demodulator including

(a) first reference means for generating a first reference signal having the first signature used to generate the first signature signal with said first signature means,

(b) a first correlation processor for generating a first correlation output signal related to the first signature signal communicated with said first communicating means by correlating the combination signature signal generated with said combining means and the first reference signal generated with said first reference means,

(c) second reference means for generating a second reference signal having the second signature used to generate the second signature signal with said second signature means,

(d) a second correlation processor for generating a second correlation output signal related to the second signature signal communicated with said second communicating means by correlating the combination signature signal generated with said combining means and the second reference signal generated with said second reference means,

(e) first output means for outputting the first correlation output signal generated with said first correlation processor, and

(f) second output means for outputting the second correlation output signal generated with said second correlation processor.

38. A discrete Fourier transform processor comprising:

input means for generating input signal samples;

reference means for generating discrete Fourier transform reference signal samples;

output means for storing discrete Fourier transformed output signal samples;

product means for generating discrete Fourier transformed product signal samples by multiplying a single input signal sample generated with said input means by a plurality of the discrete Fourier transform reference signal samples generated with said reference means before multiplying another input signal sample generated with said input means by a discrete Fourier transform reference signal sample generated with said reference means; and

update means for updating the discrete Fourier transformed output signal samples stored in said output means by adding the discrete Fourier transformed product signal samples generated with said product means and the discrete Fourier transformed output signal samples stored in said output means.

39. A Fourier transform processor comprising:

input means for generating a first plurality of input signal samples;

reference means for generating Fourier transform reference signal samples;

output means for storing a second plurality of Fourier transformed output signal samples, wherein said second plurality is different from said first plurality;

product means for generating a second plurality of Fourier transformed product signal samples by multiplying each of the first plurality of input signal samples generated with said input means by a second plurality of the Fourier transform reference signal samples generated with said reference means before multiplying another one of the first plurality of input signal samples generated with said input means by a Fourier transform reference signal sample generated with said reference means; and

update means for updating each one of the second plurality of Fourier transformed output signal samples stored in said output means by adding a corresponding one of the second plurality of Fourier transformed product signal samples generated with said product means and the corresponding one of the Fourier transformed output signal samples stored in said output means.

40. A Fourier transform processor comprising:

input means for generating input signal samples having space therebetween, where at least one space between input signal samples is greater then at least one other space between input signal samples;

reference means for generating Fourier transform reference signal samples;

output means for storing Fourier transformed output signal samples;

product means for generating Fourier transformed product signal samples by multiplying the input signal samples generated with said input means by the Fourier transform reference signal samples generated with said reference means before multiplying another input signal sample generated with said input means by a Fourier transform reference signal sample generated with said reference means; and

update means for updating the Fourier transformed output signal samples stored in said output means by adding Fourier transformed product signal samples generated with said product means and Fourier transformed output signal samples stored in said output means.

41. A Fourier transform processor comprising:

input means for generating input signal samples;

reference means for generating Fourier transform reference signal samples;

output means for storing Fourier transformed output signal samples having space therebetween, where at least one space between output signal samples is greater then at least one other space between output signal samples;

product means for generating Fourier transformed product signal samples by multiplying the input signal samples generated with said input means by the Fourier transform reference signal samples generated with said reference means before multiplying another input signal sample generated with said input means by a Fourier transform reference signal sample generated with said reference means; and

update means for updating the Fourier transformed output signal samples stored in said output means by adding Fourier transformed product signal samples generated with said product means and Fourier transformed output signal samples stored in said output means.

42. A Fourier transform processor comprising:

input means for generating a first plurality of input signal samples having space therebetween;

where at least one space between input signal samples is greater then at least one other space between input signal samples;

reference means for generating Fourier transform reference signal samples;

output means for storing a second plurality of Fourier transformed output signal samples having space therebetween, where at least one space between output signal samples is greater then at least one other space between output signal samples and where said second plurality is different from said first plurality;

product means for generating a second plurality of Fourier transformed product signal samples by multiplying each of the first plurality of input signal samples generated with said input means by a second plurality of the Fourier transform reference signal samples generated with said reference means before multiplying another one of the first plurality of input signal samples generated with said input means by a Fourier transform reference signal sample generated with said reference means; and

update means for updating each one of the second plurality of Fourier transformed output signal samples stored in said output means by adding a corresponding one of the second plurality of Fourier transformed product signal samples generated with said product means and the corresponding one of the Fourier transformed output signal samples stored in said output means.

43. A Fourier transform filter processor comprising:

input means for generating input signal samples;

reference means for generating Fourier transform reference signal samples;

product means for generating product signal samples by multiplying the input signal samples generated with said input means and the Fourier transform reference signal samples generated with said reference means;

an output memory for storing Fourier transformed output signal samples;

summing means for progressively building up magnitude of the Fourier transformed output signal samples stored in said output memory by adding the product signal samples generated with said product means to the Fourier transformed output signal samples stored in said output memory; and

output means for progressively outputting the Fourier transformed output signal samples stored in said output memory as the Fourier transformed output signal samples stored in said output memory is being progressively built up in magnitude.

44. A frequency domain transform processor comprising:

input means for sequentially generating input signal samples;

frequency domain transform reference means for storing frequency domain related reference signal samples;

an output memory for storing frequency domain signal samples; and

update means for updating the frequency domain signal samples stored in said output memory in response to each one of the input signal samples as each one of the input signal samples is sequentially generated with said input means and before another one of the input signal samples is sequentially generated with said input means, said update means including

(a) frequency domain product means for generating frequency domain product signal samples by multiplying each of the input signal samples generated with said input means and the frequency domain transform reference signal samples generated with said frequency domain transform reference means and

(b) summing means for adding the frequency domain product signal samples generated with said frequency domain product means to the frequency domain signal samples stored in said output memory means.