System for controlling key storage unit which controls access to main storage

• US 4,589,064 A
• Filed: 02/25/1983
• Issued: 05/13/1986
• Est. Priority Date: 02/27/1982
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Chiba, Takashi, Koga, Satoru, Senda, Minji
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/469,817
• Time in Patent Office: 1,173 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/164
• CPC Class Codes: G06F 12/1466 Key-lock mechanism

Abstract

A data processing apparatus includes at least one processing unit, a main storage unit, a main storage control unit, a key storage unit and a key storage control unit. The main storage unit is divided into blocks and the key storage unit stores main storage protection keys, each of which corresponds to one of the blocks of the main storage unit. Key storage access requests are received from a processing unit or the main storage control unit by the key storage control unit whenever data is to be read from or written to a block of main storage. The key storage control unit registers the key storage access requests in a key queue, prevents duplicate access requests from being registered, and processes the queued key storage access requests. The processing of key storage access requests includes updating the contents of the key storage unit to maintain a record of accesses to the main storage unit and controlling accesses to the main storage unit by permitting or denying access thereto.

Claims

1. A system for controlling a key storage unit in a data processing apparatus, comprising:

a main storage unit having at least one block;

a key storage unit for storing a main storage protection key, at least one reference bit, and at least one change bit for each block of said main storage unit;

a processing unit, said processing unit producing at least one access request for said main storage unit;

a main storage control unit, operatively connected to said main storage unit and said processing unit, for processing the access request for said main storage unit and producing a key storage access request for said key storage unit, said key storage access request having address data and requesting a change in the reference bit and the change bit in said key storage unit, the reference bit and the change bit corresponding to the accessed block of said main storage, said main storage control unit supplying said key storage access request for said key storage unit every time said main storage control unit accesses said main storage unit in response to the access request for said main storage unit supplied from said processing unit;

a key storage control unit, operatively connected to said processing unit and said main storage control unit, for controlling access to said key storage unit, comprising;

a key queue, operatively connected to said main storage control unit and said key storage unit, for temporarily holding a plurality of said key storage access requests supplied from said main storage control unit, said key storage control unit registering each of said key storage access requests supplied from said main storage control unit into said key queue in order, and said key storage control unit, independent of the above-mentioned registering process, reading and processing each of said key storage access requests registered in said key queue in order;

comparing means, operatively connected to said key queue and said main storage control unit, for comparing the content of said key storage access request supplied from said main storage control unit with the content of each key storage access request registered in said key queue; and

inhibiting means, operatively connected to said comparing means and said key queue, for inhibiting said key storage access request supplied from said main storage control unit from being registered in said key queue when the content of said key storage access request supplied from said main storage control unit is equal to the content of one of said key storage access requests registered in said key queue.

2. A system for controlling a key storage unit as defined in claim 1, wherein said key queue has n unit memories, each of said unit memories storing address data, a reference bit, and a change bit.

3. A system for controlling a key storage unit as defined in claim 2,

wherein said processing unit is capable of producing key commands as said key storage access request for said key storage unit,

wherein the at least one access request for said main storage includes a fetch access request and a store access request, and

wherein said key storage control unit further comprises decoding means, operatively connected to said main storage control unit, said processing unit and said inhibiting means, for decoding said key storage access request supplied from said main storage control unit or said processing unit, and for determining whether said key storage access request from one of said main storage control unit and said processing unit is a main storage data fetch command applied from said main storage control unit to said key storage control unit in accordance with the fetch access request for said main storage unit from said processing unit, a main storage data store command applied from said main storage control unit to said key storage control unit in accordance with the storage access request for said main storage unit from said processing unit, or one of the key commands for said key storage unit from said processing unit.

4. A system for controlling a key storage unit as defined in claim 3, wherein the key commands comprise:

an insert storage key command for reading the main storage protection key in said key storage unit;

a set storage key command for placing the main storage protection key in said key storage unit; and

p1 a reset reference bit command for resetting said reference bit in said key storage unit.

5. A system for controlling a key storage unit as defined in claim 4,

wherein said reset reference bit command has an address portion, and

wherein when the reset reference bit command is supplied to said key storage control unit, the address portion of the reset reference bit command is compared with the address data of said key storage access requests registered in said key queue, and if the address portion of the reset reference bit command is equal to the address data of one of said registered key storage access requests, the reference bit at the corresponding address of said key storage unit is reset and at the same time, the change bit at the same address of said key storage unit is changed as requested in said registered kdy storage access request.

6. A key storage control system for controlling a key storage unit, operatively connected to a processing unit, and a main storage control unit, a key storage access request being supplied to said key storage control system by one of the processing unit and the main storage control unit, said key storage control system comprising:

queuing means, operatively connected to the processing unit, the main storage control unit and the key storage unit, for adding the key storage access request to in-queue access requests; and

control means, operatively connected to said queuing means, for comparing the in-queue access requests with the key storage access request, for preventing queuing of the key storage access request when the key storage access request matches one of the in-queue access requests, and for processing the in-queue access requests.

7. A key storage control system as set forth in clam 6, wherein said queuing means comprises:

a key register, operatively connected to the central processing unit, the channel processing unit, the main storage control unit and said control means, having an operation code portion, an address portion and a key data portion;

a key queue comprising n unit memories, each of said unit memories comprising;

an address portion operatively connected to the address portion of said key register;

a reference bit portion operatively connected to said control means;

a change bit portion operatively connected to said control means;

a validity bit portion operatively connected to said control means; and

a key storage access request bit portion operatively connected to said control means;

first comparing means, operatively connected to said key register, said key queue and said control means, for comparing the address portion of said key register with the address portion in each of said unit memories of said key queue, said comparing means comprising n comparing circuits;

an in-queue counter, operatively connected to said key queue, for counting the key storage access requests as they enter said key queue;

a selector, operatively connected to said key queue and said control means, for selecting one of the key storage access requests to be executed;

an out-queue counter, operatively connected to said selector, for counting key storage access requests as they are executed;

second comparing means, operatively connected to said in-queue counter, said out-queue counter and said control means, for providing a queue-full signal and a queue-empty signal; and

a key-storage access reqister, operatively connected to said key register, said key queue, said out-queue counter and said selector, for supplying the key storage access request to the key storage unit.

8. A key storage control system as set forth in claim 7, within said control means comprises:

a decoder, operatively connected to the operation code portion of said key register, for decoding the contents of the operation code portion of said key register;

key register busy means, operatively connected to said key register and said decoder, for generating a key register busy signal;

key-storage access register busy means, operatively connected to said key register, said decoder and said key register busy means, for generating a key-storage access register busy signal;

entry locating means, operatively connected to said key queue and said first comparing means, for generating signals indicating whether a matching entry, having an address portion which matches the address portion of said key register, exists in said key queue and signals indicating whether the matching entry has a request bit equal to a first value;

reference bit means, operatively connected to said key queue and said entry locating means, for generating a signal indicating that the matching entry has a reference bit equal to the first value and a change bit equal to the first value and for generating a signal indicating that the matching entry has a reference bit equal to the first value and a change bit equal to a second value;

queue register signal means, operatively connected to said second comparing means, said decoder, said key-storage access register busy means, said entry locating means and said reference bit means, for generating a queue register signal which has a logic value equal to the first value if said entry locating means indicates that the matching entry is not in said key queue, said second comparing means indicates that said key queue is not full and said decoder indicates that the contents of the operation code portion in said key register is a data fetch command or a data store command, or said entry locating means indicates that the matching entry is in said key queue, said second comparing means indicates that said key queue is not full, said decoder indicates that the contents of the operation code portion of said key register is a data store command and said reference bit means indicates that the reference bit equals the first value and the change bit equals the second value for the matching entry;

set signal means, operatively connected to said in-queue counter, said key queue and said queue register signal means, for generating signals which set validity and request bits in said key queue;

request bit reset means, operatively connected to said key queue, said out-queue counter and said key-storage access register busy means, for generating signals which reset the request bits in said queue; and

validity bit reset means, operatively connected to said key queue, said second comparing means, said decoder, said entry locating means, said reference bit means and said set signal means, for generating signals which reset the validity bits in said key queue.