Chirp signal gating circuit for expander in a pulse compression radar system
First Claim
1. A gating circuit for an expander in a pulse compression radar system which includes a surface acoustic wave delay line responsive to an input pulse to generate a frequency-modulated radio-frequency output signal, said gating circuit comprising:
- a gate having an input to which the output signal from the delay line is applied;
means responsive to the output signal from the delay line for generating a digital pulse corresponding to each cycle of the output signal;
a digital counter operable to count the digital pulses and hvaing at least first and second predetermined counter states; and
control means connected to said digital counter and to said gate, said control means being responsive to the first predetermined counter state to open said gate, and responsive to the second predetermined counter state to close said gate.
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Accused Products
Abstract
A gating arrangement for a pulse compression circuit includes a surface acoustic wave delay line SAW responsive to an input pulse to generate a frequency-modulated radio-frequency output signal which is applied to an output gate OG. The output signal is also applied to circuit means DC operable to product a digital pulse corresponding to each cycle of the output signal. The pulses are counted by a counter CT and applied to control means CM. This responds to first and second predetermined counter states to control the operation of the output gate OG.
6 Citations
4 Claims
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1. A gating circuit for an expander in a pulse compression radar system which includes a surface acoustic wave delay line responsive to an input pulse to generate a frequency-modulated radio-frequency output signal, said gating circuit comprising:
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a gate having an input to which the output signal from the delay line is applied; means responsive to the output signal from the delay line for generating a digital pulse corresponding to each cycle of the output signal; a digital counter operable to count the digital pulses and hvaing at least first and second predetermined counter states; and control means connected to said digital counter and to said gate, said control means being responsive to the first predetermined counter state to open said gate, and responsive to the second predetermined counter state to close said gate. - View Dependent Claims (2, 3, 4)
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Specification