Recirculating MOS charge pump

• US 4,621,315 A
• Filed: 09/03/1985
• Issued: 11/04/1986
• Est. Priority Date: 09/03/1985
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Peterson, Joe W., Vaughn, Herchel A.
• Primary Examiner(s): Beha, Jr., William H.
• Application Number:
  US06/771,919
• Time in Patent Office: 427 Days
• Field of Search: 363/59, 363/60, 320/1
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

Claims

1. A circuit for increasing a power supply voltage from a power supply source and providing a boosted output voltage at an output terminal, comprising:

diode means coupled between a first node and a supply terminal adapted to receive the power supply voltage, said diode means having a threshold voltage and preventing current flow from the first node to the supply terminal;

first charge storage means coupled to the output terminal for selectively storing the power supply voltage and a boost voltage to provide the boosted output voltage; and

transistor coupling means having a control electrode, a first current electrode coupled to the first node, and a second current electrode coupled to the output terminal, and a threshold voltage associated therewith;

wherein the improvement comprises;

compensation means coupled between the first node and the control electrode of the transistor coupling means, for providing a control voltage to the control electrode sufficiently above the threshold voltage of the transistor coupling means so as to reduce the effective threshold voltage drop between the first node and the output terminal to substantially zero volts.

2. The circuit of claim 1 wherein said compensation means further comprises:

second compensation means coupled between the supply terminal and the first node, for preventing the first node from dropping below the power supply voltage.

3. The circuit of claim 2 wherein said second compensation means further comprises:

a first transistor having its current conducting electrodes coupled between the supply terminal and the output terminal, and having a control electrode coupled to a first node;

a second transistor having its current conducting electrodes coupled between the supply terminal and the first node, and having a control electrode coupled to the output terminal; and

second charge storage means coupled to the first node for selectively storing the boost voltage.

4. The circuit of claim 1 wherein said compensation means further comprise means coupled between a predetermined one of the current electrodes of the transistor coupler and the control electrode of the transistor coupler, for cancelling the threshold voltage drop of the transistor coupler and making said threshold voltage drop substantially zero volts, comprising:

second charge storage means coupled between the output node and the control electrode of the transistor coupler;

a first diode configured transistor having both a first current electrode and a control electrode connected to the output terminal, and a second current electrode;

a second diode configured transistor having a first current electrode coupled to the output terminal, and both a second current electrode and a control electrode connected to the control electrode of the transistor coupler;

a third diode configured transistor having a first current electrode coupled to the control electrode of the transistor coupler, and both a second current electrode and a control electrode connected together; and

third charge storage means coupled to the second current electrodes of the first and third diode configured transistors, for selectively storing the boost voltage.

5. The circuit of claim 1 further comprising:

clock means for receiving an input clock signal and providing therefrom a control signal and a complement thereof as the boost voltage to the charge storage means and to the compensation means, respectively.

6. A charge pump circuit for boosting a power supply voltage to provide a boosted output voltage, comprising:

a diode configured transistor having a first current electrode and a control electrode connected together and coupled to a terminal for receiving the power supply voltage, and a second current electrode connected to a first node for supplying a primary voltage at the first node, said diode configured transistor having a first threshold voltage drop associated therewith;

first capacitance means having a first electrode coupled to the first node and a second electrode for selectively receiving a clock signal voltage, said capacitance means boosting the primary voltage at the first node to a secondary voltage;

first compensation means coupled in parallel with the diode configured transistor for compensating for the first threshold voltage drop so that the primary voltage substantially equals the power supply voltage;

output capacitance means for selectively storing the secondary voltage to provide the boosted output voltage;

transistor coupler means having a second threshold voltage drop associated therewith, said transistor coupler means having a control electrode and current conducting electrodes which selectively couple the first node to the output capacitance means; and

second compensation means coupled between the control electrode and a predetermined one of the current conducting electrodes of the transistor coupler means for compensating for the second threshold voltage drop so that the boosted output voltage substantially equals the secondary voltage at the first node.

7. The charge pump of claim 6 wherein the first compensation means comprise:

a first transistor having a first current electrode coupled to the terminal for receiving the power supply voltage, a control electrode and a second current electrode coupled to the first node;

a second transistor having a first current electrode coupled to the terminal for receiving the power supply voltage, a control electrode coupled to the first node, and a second current electrode coupled to the control electrode of the first transistor; and

second capacitance means having a first electrode coupled to the second current electrode of the second transistor, and a second electrode for selectively receiving the clock signal voltage.

8. The charge pump of claim 6 wherein the second compensation means further comprise:

second capacitance means having a first electrode coupled to the first node and a second electrode coupled to the control electrode of the transistor coupler means;

a first diode configured transistor having a first current electrode coupled to the first node and both a control electrode and a second current electrode coupled to the control electrode of the transistor coupler means;

a second diode configured transistor having a first current electrode coupled to the control electrode of the transistor coupler means, and both a control electrode and a second current electrode connected together;

a third diode configured transistor having both a first current electrode and a control electrode coupled to the first node, and a second current electrode coupled to the second current electrode of the second diode configured transistor; and

third capacitance means having a first electrode coupled to the second current electrodes of the second and third diode configured transistors, and a second electrode for selectively receiving the clock signal voltage.

9. The charge pump of claim 7 wherein the second capacitance means selectively receives the clock signal voltage by receiving a delayed complement of the clock signal voltage.

10. The charge pump of claim 8 wherein the third capacitance means selectively receives the clock signal voltage by receiving a delayed complement of the clock signal voltage.

11. A method of providing a boosted output voltage from a power supply voltage, comprising the steps of:

coupling a power supply voltage terminal to a first node via a diode means having a first threshold voltage drop associated therewith;

coupling charge storage means to the first node for selectively boosting the first node'"'"'s voltage potential to a predetermined voltage potential;

selectively coupling the first node to an output charge storage means via a coupling device having a second threshold voltage drop associated therewith; and

compensating for the second threshold voltage drop so that the voltage potential coupled to the output charge storage means substantially equals the voltage potential of the first node.

12. The method of claim 11 further comprising the step of:

compensating for the first threshold voltage drop of the diode means so that the first node has the same voltage potential as the power supply voltage terminal.