Multiprocessor computing system featuring shared global control

• US 4,626,634 A
• Filed: 09/30/1982
• Issued: 12/02/1986
• Est. Priority Date: 09/30/1982
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Brahm, David J., Hepler, Edward L., Grinn, James M., Schan, Edward P. Jr.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/430,681
• Time in Patent Office: 1,524 Days
• Field of Search: 364/200, 364/900, 179/18 ES, 179/2 DP, 179/175.2 D
• US Class Current: 379/28
• CPC Class Codes: G06F 12/0692 Multiconfiguration, e.g. local and global addressing

Abstract

A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space; a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station'"'"'s station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.

Claims

1. In a data processing communication or telephone system, a multiprocessor comprising:

a plurality of stations, each having a first plurality and a second plurality of addresses associated therewith, the addresses of the first plurality of addresses of each station being exclusive to that station and the addresses of the second plurality of addresses being common to the stations;

each station including a plurality of addressable elements, each element having a first address from the first plurality of addresses and a second address from the second plurality of addresses associated therewith;

the plurality of elements of each station including a plurality of common elements each having a functional counterpart common element in at least one other station, each common element and it counterpart common elements having the same second address associated with them;

a system communication medium interconnecting the plurality of stations;

each station including a station communication medium interconnecting the plurality of elements of the associated station;

at least two of the plurality of stations each including element accessing means for selectively generating the first address of an element of another station on the system medium to access the element of the other station, and for selectively generating the second address of an element of the associated station on the station medium of the associated station to access the element of the associated station; and

each station including first interface means for connecting the system medium with the station medium of the associated station in response to detecting an address from the first plurality of addresses of the associated station on the system medium.

2. The system of claim 1 wherein the element accessing means include:

means for selectively generating the first address of an element of another station on the station medium of the associated station; and

second interface means for connecting the system medium with the station medium of the associated station in response to detecting an address from the first plurality of addresses of another station on the station medium.

3. The system of claim 2 wherein the elements of each station include means responsive to being selectively accessed for inhibiting the second interface means from connecting the station medium with the system medium.

4. The system of claim 1 wherein

each address of the second plurality of addresses is uniquely paired with an address in each of the first pluralities of addresses, and wherein

each first interface means include means for converting an address from the first plurality of addresses of the associated station present on the system medium into the paired address from the second plurality of addresses and for generating the paired address on the station medium of the associated station.

5. The system of claim 1 wherein the first plurality of addresses of each station includes the addresses of the second plurality of addresses each combined with an address portion identifying the associated station.

6. The system of claim 1 wherein each address of the first plurality of addresses of each station includes an address of the second plurality of addresses in combination with an address portion identifying the associated station.

7. The system of claim 5 or 6 wherein the first interface means of each station include means for converting an address from the first plurality addresses of the associated station present on the system medium into the included address from the second plurality of addresses and for generating the included address on the station medium of the associated station.

8. The system of claim 1 wherein each of the at least two stations further includes means for preventing the element accessing means of the associated station from accessing elements in response to detecting an address from the first plurality of addresses of the associated station on the system medium.

9. The system of claim 1 wherein each of the at least two stations further includes means for preventing the element accessing means of the associated station from generating an address on a medium in response to detecting an address from the first plurality of addresses of the associated station on the system medium.

10. The system of claim 8 or 9 wherein the preventing means are included in the first interface means.

11. The system of claim 2 wherein the element accessing means are selectively connected to the second medium, and wherein each of the at least two stations further include means for disconnecting the element accessing means from the second medium in response to detecting an address from the first plurality of addresses of the associated station on the first medium.

12. The system of claim 1 wherein each of the at least two stations further comprises:

means for detecting accessing of an element of the associated station by element accessing means of another station while the element accessing means of the associated station are accessing an element; and

means responsive to the detecting means for pausing accessing by the element accessing means of the associated station, and for continuing accessing by the element accessing means of the associated station when the element accessing means of the other station cease accessing the element of the associated station.

13. The system of claim 1 wherein each station further includes means, responsive to detecting an address from the first plurality of addresses of the associated station on the system medium, for generating an acknowledgement signal on the first medium, and wherein

each of the at least two stations further includes access control means, responsive to detecting on the system medium an acknowledgement signal generated in response to generation by the associated element accessing means of the acknowledged address, for enabling the associated element accessing means to continue accessing.

14. The system of claim 1 wherein the element accessing means of each of the at least two stations include processor means, and wherein the plurality of elements of each of the at least two stations include means responsive to being selectively accessed for interrupting the processor means.

15. The system of claim 1 wherein at least one station of the plurality of stations includes means for generating a pause signal on the system medium, and wherein each of the at least two stations includes means responsive to detecting the pause signal for halting the associated element accessing means.

16. The system of claim 1 wherein the element accessing means of each of the at least two stations make transitions between a plurality of states, wherein at least one station of the plurality of stations includes means for generating a pause signal on the system medium, and wherein each of the at least two stations includes means responsive to detecting the pause signal for stopping the element accessing means from making a transition from their current state.

17. The system of claim 1 wherein at least one station of the plurality of stations includes means for generating a pause signal on the system medium and wherein each station includes least one element that makes transitions between a plurality of states and means responsive to detecting the pause signal for stopping the at least one element that makes transitions from making a transition from its current state.

18. The system of claim 1 wherein the element accessing means of each of the at least two stations make transitions between a plurality of states including a first state, wherein each station of the plurality of stations includes means for generating a reset signal on the system medium, and wherein each of the at least two stations includes reset means responsive to detecting the reset signal for causing the associated element accessing means to make the transition into the first state, the reset means further responsive to being selectively accessed for causing the associated element accessing means to make the transition into the first state.

19. The system of claim 1 wherein each station includes at least one element that makes transitions between a plurality of states including a first state, means for generating a reset signal on the system medium, and reset means responsive to detecting the reset signal on the system medium for forcing the at least one element that makes transitions to make the transition into the first state, the reset means further responsive to being selectively accessed for forcing the at least one element that makes transitions to make the transition into the first state.

20. The system of claim 1 wherein at least one of the at least two stations includes processor means for executing diagnostic programs and wherein each station of the plurality of stations includes diagnostic memory means for storing a diagnostic program for diagnosing the station means for generating a diagnose signal on the system medium, and diagnose means responsive to detecting the diagnose signal for causing a processor means to execute the diagnostic program of the station, the diagnose means further responsive to being selectively accessed for causing the processor means to execute the diagnostic program of the station.

21. The system of claim 20 wherein the diagnostic memory means are selectively removable from the stations.

22. The system of claim 1 wherein at least one station of the plurality of stations includes storage means for storing a boot program for booting the system, means for executing the boot program, and means responsive to being selectively accessed for causing the executing means to execute the boot program.

23. The system of claim 1 wherein each station of the plurality of stations includes storage means for storing information describing the station, the storage means of all stations being for selective access by the accessing means of a station to determine the configuration of the system.