Master-slave microprocessor control circuit

• US 4,633,039 A
• Filed: 04/11/1984
• Issued: 12/30/1986
• Est. Priority Date: 12/29/1980
• Status: Expired due to Fees

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Communication Systems Corporation (Verizon Communications Inc.)
• Inventors: Holden, James R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/599,122
• Time in Patent Office: 993 Days
• Field of Search: 364/200, 364/900, 364/300, 179/18 ES, 179/18 EE
• US Class Current: 379/32.01
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1654 where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: H04Q 3/545 using a stored programme

Abstract

A control circuit, for use in a telephone switching system, which monitors, controls and transfers data to and from memory, input-output devices and external circuits. A pair of microprocessors and associated read-only and random-access memories are operated in a master-slave arrangement. A comparison circuit continuously monitors the integrity of the master microprocessor by comparing the signal on its data, address and control leads with those of a slave microprocessor.

Claims

1. A processor control circuit for use in a telephone switching system, said telephone switching system being operative to provide external address data and control signals and an interrupt signal, said processor control circuit comprising:

first processing means operated to generate a first group of internal address, data and control signals;

second processing means operated in sychronism with said first processing means to generate a second group of internal address, data and control signals; and

comparison means connected to said first and second processing means, operated in response to miscomparison between said first and second groups of internal address, data and control signals to generate a processor failure signal;

said first and second processing means operated in a master-slave arrangement, wherein only said first group of internal address, data control signals is applied to said telephone switching system, and wherein said first and second processing means are both operated to receive said external address, data and control signals;

whereby said second processing means is operated as a receive-only processing means with respect to said telephone switching system;

a master bus transceiver connected to said first processing means;

a slave bus transceiver connected to said second processing means;

a system data bus connected to said master and slave bus transceivers;

said master bus transceiver operated in response to a first predetermined pattern of said first group of internal address and control signals to transfer said first group of internal data signals to said system data bus;

a local bus transceiver connected to said system data bus and said first processing means; and

an input-output device connected to said local bus transceiver and said first processing means;

said local bus transceiver operated in response to a second predetermined pattern of said first group of internal address and control signals to transfer data from said system data bus to said local bus transceiver;

said input-output device operated in response to a third predetermined pattern of said first group of internal address and control signals to transfer data from said local bus transceiver to said input-output device;

said input-output device further operated in response to a fourth predetermined pattern of said first group of internal address and control signals to transfer data to said local bus transceiver;

said local bus transceiver operated in response to a fifth predetermined pattern of said first group of internal address and control signals to transfer data from said input-output device to said system data bus;

said master bus transceiver operated in response to a sixth predetermined pattern of said first group of internal address and control signals to transfer data from said system data bus to said first processing means;

said slave bus transceiver operated in response to a first predetermined pattern of said second group of internal address and control signals to transfer data from said system data bus to said second processing means;

said input-output device comprising;

a programmable interrupt controller connected to said telephone switching system and said first processing means, operated in response to said data from said local bus transceiver to arrange an interrupt recognition sequence;

said programmable interrupt controller further operated in response to said interrupt signal to generate an interrupt received signal;

said first processing unit further operated in response to said interrupt received signal to generate an interrupt acknowledge signal;

said programmable interrupt controller further operated in response to said interrupt acknowledge signal and said fourth pattern of said first group of internal address and control signals to transfer interrupt identification data to said local bus transceiver.

2. A processor control circuit as claimed in claim 1, wherein:

said comparison means comprises an address comparator operated in response to miscomparisons between said first and second groups of address signals to generate an address failure signal.

3. A processor control circuit as claimed in claim 1, wherein:

said comparison means further comprises a data comparator operated in response to miscomparisons between said first and second data signals to generate a data failure signal.

4. A processor control circuit as claimed in claim 1, wherein:

said comparison means further comprises a control signal comparator operated in response to miscomparisons between said first and second groups of control signals to generate a control failure signal.

5. A processor control circuit as claimed in claim 1, wherein there is further included:

address parity means connected to said first processing means, operated in response to even parity across said first group of internal address signals to generate an address parity failure signal.

6. A processor control circuit as claimed in claim 1, wherein there is further included:

data parity means connected to said first processing means operated in response to even parity across said first group of data signals to generate a data parity failure signal.

7. A processor control circuit as claimed in claim 1, wherein said telephone switching system is operated to generate a clock signal, said processor control circuit further comprising:

clock monitor means operated in response to an absence of said clock signal for a predetermined time to generate a clock failure signal.

8. A processor control circuit as claimed in claim 1, wherein said telephone switching system is operated to generate a ready signal, said control circuit further comprising:

ready signal monitor means operated in response to an absence of said ready signal for a predetermined time to generate a ready failure signal.

9. A processor control circuit as claimed in claim 2, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate an address comparator routining signal;

said address comparator further operated in response to said address comparator routining signal to generate said address failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said address failure signal to generate a self check failure signal.

10. A processor control circuit as claimed in claim 3, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate a data comparator routining signal;

said data comparator further operated in response to said data comparator routining signal to generate said data failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said data failure signal to generate a self check failure signal.

11. A processor control circuit as claimed in claim 4, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate a control signal routining signal;

said control signal comparator further operated in response to said control signal routining signal to generate said control failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said control failure signal to generate a self check failure signal.

12. A processor control circuit as claimed in claim 5, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate an address parity routining signal;

said address parity means further operated in response to said address parity routining signal to generate said address parity failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said address parity failure signal to generate a self check failure signal.

13. A processor control circuit as claimed in claim 6, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate a data parity routining signal;

said data parity means further operated in response to said data parity routining signal to generate said data parity failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said data parity failure signal to generate a self check failure signal.

14. A processor control circuit as claimed in claim 7, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate a clock monitor routining signal;

said clock monitor means further operated in response to said clock monitor routining signal to generate said clock failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said clock failure signal to generate a self check failure signal.

15. A processor control circuit as claimed in claim 8, wherein there is further included:

self check means operated in response to a predetermined pattern of said first group of address, data and control signals to generate a ready monitor routining signal;

said ready signal monitor means further operated in response to said ready monitor routining signal to generate said ready failure signal;

said self check means further operated in response to said predetermined pattern and an absence of said ready failure signal to generate a self check failure signal.