Self configuring bus structure for computer network

• US 4,635,192 A
• Filed: 12/06/1983
• Issued: 01/06/1987
• Est. Priority Date: 12/06/1983
• Status: Expired due to Fees

• Current Assignee: TRI Sigma Corporation
• Original Assignee: TRI Sigma Corporation
• Inventors: Mioduski, Paul C., Ceccon, Claude R.
• Primary Examiner(s): WILLIAMS JR, ARCHIE E
• Application Number:
  US06/558,778
• Time in Patent Office: 1,127 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 361/415
• US Class Current: 710/301
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: H05K 7/1459 Circuit configuration, e.g. routing signals

Abstract

A computer bus structure includes a plurality of separate bus segments on a mother board. Plugging in of each of a plurality of interface boards automatically connects the right-hand portion of a particular bus segment to the left-hand portion of an adjacent bus segment so that a local bus of the needed length is created from the separate bus segments by the plugging of a processor board and a plurality of interface boards into successive adjacent connector slots, respectively, of the mother board. Insertion of processor boards into a particular connection slot of the mother board prevents the two bus segments adjacent thereto from being connected.

Claims

1. A reconfigurable bus structure in a system including a first processor and a first group of interface circuits for connection to said first processor, said first processor and each of said interface circuits each being in electrical communication with a plurality of edge connector conductors, said reconfigurable bus structure comprising in combination:

a mother board having a plurality of edge connecting means for connection to the edge connector conductors of various ones of said interface circuits and said first processor;

a plurality of local bus segments disposed on said mother board, each of said local bus segments including a first number of conductors each having separate first and second electrical contact areas which are disposed on opposite sides of adjacent ones of said edge connecting means;

a first processor board on which said first processor is disposed, said first processor board having a second number of edge connector conductors, each of which has a first electrical contact area, for electrically contacting said first electrical contact areas of a corresponding one of said local bus segments, said second number being equal to said first number; and

a first group of interface boards on which said interface circuits of said first group are disposed, respectively, each of said interface boards having thereon a third number of edge connector conductors, each of which has a first electrical contact area for electrically contacting corresponding ones of said first electrical contact area of conductors of one of said local bus segments on a first side of one of said edge connecting means into which that interface board is plugged, each of said third number of edge connector conductors also having a second electrical contact area for electrically contacting corresponding ones of said second electrical contact areas of conductors of another one of said local bus segments on a second side of that edge connecting means, said third number being equal to said first number, wherein when said first processor board is plugged into a first edge connecting means of said mother board, the first electrical contact areas of each of the edge connector conductors of said first processor board electrically contacts corresponding ones of the first electrical contact areas of conductors of one of said local bus segments on a first side of a first one of said edge connecting means, wherein when each of said interface boards of said first group is plugged into a respective, successive one of the rest of said edge connecting means, the first electrical contact areas of the edge connector conductors of that interface board respectively electrically contact corresponding ones of the first electrical contact areas of conductors at another one of said local bus segments on a first side of of that edge connecting means, and the second electrical contact areas of the edge connector conductors of that interface board respectively electrically contact corresponding ones of the second electrical contact areas of conductors of another one of said local bus segments on a second side of that edge connecting means, whereby physical insertion of said first processor board and said interface boards of said first group into successive edge connecting means of said mother board automatically creates a local bus of the needed length operatively connecting said first processor to said interface circuits of said first group.

2. The reconfigurable bus structure of claim 1 wherein no edge connector conductor of said first processor board electrically contacts the second electrical contact area of any of said conductors of any of said local bus segments

3. The reconfigurable bus structure of claim 2 including a second processor on a second processor board similar to said first processor board and a second group of interface circuits disposed on respective ones of a second group of interface boards similar to said interface boards of said first group, said second processor board and said interface boards of said second group being plugged into successive adjacent edge connecting means of said mother board to create a second local bus that is electrically isolated from said first local bus.

4. The reconfigurable bus structure of claim 3 wherein said mother board includes a plurality of additional bus conductors which are included in a system bus which is electrically isolated from said first and second local buses, some additional electrical contact areas being disposed in each of said edge connecting means being also connected to respective corresponding conductors of said system bus, each of said first and second processor boards having additional edge connector conductors for electrically contacting said additional electrical contact areas of the slots into which said first and second processor boards are plugged.

5. A reconfigurable bus structure in a system including a mother board, a processor board having a first processor thereon, and a first interface board, the reconfigurable bus structure comprising in combination:

(a) a plurality of separate bus segments on the mother board, each of the bus segments including a plurality of separate bus conductors each having a first end and a second end;

(b) first and second sets of interface board connector conductors on the first interface board and a first set of processor board connector conductors on the processor board;

(c) processor board connecting means for plug-in connecting of the first set of processor board connector conductors to corresponding first ends of the bus conductors of a first one of the bus segments;

(d) first interface board connecting means for plug-in connecting of the first set of interface board connector conductors to corresponding second ends of the bus conductors of the first bus segments, and plug-in connecting of the second set of interface board connector conductors to corresponding first ends of the bus conductors of a second one of the bus segments; and

(e) means on the first interface board for electrically coupling the corresponding interface board conductors of the first and second sets, whereby connecting the first interface board and the processor board to the mother board creates a local bus including the first and second segments.

6. The reconfigurable bus structure of claim 5 including a second interface board having first and second sets of interface board connector conductors and second interface board connecting means for plug-in connecting of the first set of interface board connector conductors of the second interface board to corresponding second ends of the bus conductors of the second bus segment and plug-in connecting of the second set of interface board connector conductors of the second interface board to corresponding first ends of the bus conductors of a third bus segment, and means on the second interface board for electrically coupling the corresponding interface board conductors of the first end and second sets of the second interface board, whereby connecting of the second interface board to the mother board extends the local bus to include the third bus segment.

7. The reconfigurable bus structure of claim 6 wherein no processor connector conductors of the processor board is directly connected to any other bus segment than the first bus segment.