High-speed queue sequencer for a burst-switching communications system

• US 4,646,294 A
• Filed: 08/02/1985
• Issued: 02/24/1987
• Est. Priority Date: 08/02/1985
• Status: Expired due to Term

• Current Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Original Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Inventors: Rao, Pamidimukkala M. V., Eliscu, Mark, Amstutz, Stanford R.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Rokoff, Kenneth J.
• Application Number:
  US06/762,642
• Time in Patent Office: 571 Days
• Field of Search: 370/58, 370/60, 370/94, 370/104, 370/110.1
• US Class Current: 370/412
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

This invention provides a high-speed queue sequencer which may be employed as a component of a link switch or hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the queue sequencer includes a data/address bus, control including a stored program in a 64-bit wide PROM, a random-access memory for queue memory which stores administrative information pertaining to bursts passing through the switch, enque means for adding a burst to the list of bursts awaiting assignment to an output channel, and deque means for assigning the highest-priority burst on this list to an output channel and removing the burst from the list, first-in first-out memory for storing requests from switching processors and providing these requests to the control of the queue sequencer within priority class in the same time order as received, and input and output interfaces for coupling with the switching processors. A switching processor is a companion high-speed processor employed as one or more components in a link switch and hub switch. Most components of the queue sequencer operate substantially in parallel with and independently of the control, which is a contributing factor to the speed advantage realized by the queue sequencer. The queue sequencer performs queue administration for all switching processors of a link or hub switch.

Claims

1. A high-speed queue sequencer for use in a switch of a burst-switching communications system, a burst being a plurality of bytes, said system including a plurality of switches interconnected by time-division multiplexed communications links, each link having a plurality of frames within each second of time, each frame having a plurality of channels, each channel having communications capacity for the transmission of one byte, a byte being a predetermined number of bits, a bit being one binary digit, said system including a plurality of ports, each port being a component of a switch, said switch including a queue sequencer and at least one switching processor, said queue sequencer and switching processor(s) being coupled via a queue-sequencer bus, said queue sequencer comprising:

(a) a data/address bus;

(b) control means coupled with said data/address bus for controlling said queue sequencer, said control means including stored-program memory and execution means and queue-memory means for storing administrative information pertaining to bursts passing through said link switch;

(c) enque/deque means coupled with said data/address bus, said enque means for performing the administration required for placing a burst on an output queue, said output queue being a list which indicates those bursts awaiting assignment to an output channel in a communications link, said deque means for assigning the highest priority burst on an output queue to an idle output channel of said communications link and removing said assigned burst from said output queue, said enque/deque means operating substantially in parallel with and independently of said control means;

(d) request-holding means coupled with said data/address bus, for receiving requests from said switching processor(s), determining the priority of each request, storing said pending requests within priority classes, and outputting said requests within each priority class in the same time order as received, said request-holding means operating substantially in parallel with and independently of said control means;

(e) input-interface means coupled between said queue-sequencer bus and said request-holding means, for providing an interface between said queue sequencer and said switching processor(s), said input-interface means having the ability to receive a request from a switching processor of said switch and to transmit said request to said request-holding means, said input-interface means operating substantially in parallel with and independently of said control means; and

(f) output-interface means coupled between said data/address bus and said queue-sequencer bus, for providing an interface between said queue sequencer and said switching processor(s), said output interface means having the ability to transmit a buffer address to a switching processor, said output-interface means operating substantially in parallel with and independently of said control means;

(g) whereby said queue sequencer operates substantially in parallel with and independently of said switching processor(s), and said queue sequencer acts on behalf of all switching processors of said switch.

2. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 1 wherein the transmission speeds over said communications links are substantially equivalent to the T1 rate or a higher rate.

3. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 1 wherein a byte is eight bits.

4. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 1 wherein said request-holding means comprises one or more first-in first-out memories, each of said memories including the required control functions.

5. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 1 wherein said stored-program memory is a programmable read-only memory having a word length of at least sixty-four bits.

6. A high-speed queue sequencer for use in a switch of a burst-switching system as described in claim 1 wherein said queue-memory means is a random-access memory coupled with said data/address bus and said control means.

7. A high-speed queue sequencer for use in a switch of a burst-switching system as described in claim 1 wherein said communications system includes a link switch and said queue sequencer is a component of said link switch.

8. A high-speed queue sequencer for use in a switch of a burst-switching system as described in claim 1 wherein said communications system includes a hub switch and said queue sequencer is a component of said hub switch.

9. A high-speed queue sequencer for use in a switch of a burst-switching communications system, a burst being a plurality of bytes, a byte being a predetermined number of bits, a bit being one binary digit, said system including a link switch having a plurality of ports, each port being a component of said switch, each port being associated with a communications channel, said link switch including a queue sequencer and at least one switching processor, said queue sequencer and switching processor(s) being coupled via a queue-sequencer bus, said queue sequencer comprising:

(a) a data/address bus;

(b) control means coupled with said data/address bus for controlling said queue sequencer, said control means including stored-program memory and execution means and queue-memory means for storing administrative information pertaining to bursts passing through said link switch;

(c) enque/deque means coupled with said data/address bus, said enque means for performing the administration required for placing a burst on an output queue, said output queue being a list which indicates those bursts awaiting assignment to an output channel, said deque means for assigning the highest priority burst on an output queue to an idle output channel and removing said assigned burst from said output queue, said enque/deque means operating substantially in parallel with and independently of said control means;

(d) request-holding means coupled with said data/address bus, for receiving requests from said switching processor(s), determining the priority of each request, storing said pending requests within priority classes, and outputting said requests within each priority class in the same time order as received, said request-holding means operating substantially in parallel with and independently of said control means;

(e) input-interface means coupled between said queue-sequencer bus and said request-holding means, for providing an interface between said queue sequencer and said switching processor(s), said input-interface means having the ability to receive a request from a switching processor of said link switch and to transmit said request to said request-holding means, said input-interface means operating substantially in parallel with and independently of said control means; and

(f) output-interface means coupled between said data/address bus and said queue-sequencer bus, for providing an interface between said queue sequencer and said switching processor(s), said output interface means having the ability to transmit a buffer address to a switching processor, said output-interface means operating substantially in parallel with and independently of said control means;

(g) whereby said queue sequencer operates substantially in parallel with and independently of said switching processor(s), and said queue sequencer acts on behalf of all switching processors of said link switch.

10. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 9 wherein a byte is eight bits.

11. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 9 wherein said request-holding means comprises one or more first-in first-out memories, each of said memories including the required control functions.

12. A high-speed queue sequencer for use in a switch of a burst-switching communications system as described in claim 9 wherein said stored-program memory is a programmable read-only memory having a word length of at least sixty-four bits.

13. A high-speed queue sequencer for use in a switch of a burst-switching system as described in claim 9 wherein said queue-memory means is a random-access memory coupled with said data/address bus and said control means.

14. A high-speed queue sequencer for use in a switch of a burst-switching system as described in claim 9 wherein said communications system includes a link switch and said queue sequencer is a component of said link switch.

15. A high-speed queue sequencer for a burst-switching system as described in claim 9 wherein said communications system includes a hub switch and said queue sequencer is a component of said hub switch.