Vector data processor

• US 4,651,274 A
• Filed: 03/28/1984
• Issued: 03/17/1987
• Est. Priority Date: 07/21/1980
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Torii, Shunichi, Nagashima, Shigeo, Omoda, Koichiro
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/594,301
• Time in Patent Office: 1,084 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/8
• CPC Class Codes: G06F 15/8084 Special arrangements thereof, e.g. mask or switch
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the vector index register to form addresses of data, thereby to execute the consecutive reading of the data from a main storage and the consecutive writing thereof into the main storage with an increased processing speed by generating addresses and storing data in overlapping operations.

Claims

1. A vector data processor, comprising:

(a) a main storage;

(b) operation means for sequentially performing an operation on vector elements provided to said operation means in such a manner as to provide vector elements corresponding to the results of said operation in parallel to receiving new vector elements;

(c) a plurality of vector registers each being selected by an instruction, each being accessible independently from each other vector register, and each including means connected to said main storage and said operation means so as to receive vector elements therefrom or to provide vector elements thereto for holding a plurality of vector elements at a plurality of address locations within each vector register;

(d) control means connected to control said vector registers and responsive to instructions, including a plurality of write counter means each connected to a corresponding vector register, for sequentially indicating addresses of said storage locations within the corresponding vector register at which a write operation is to be effected for vector elements received by the corresponding vector register when the corresponding vector register is selected by an instruction so as to receive the vector elements, and including a plurality of read counter means each connected to a corresponding vector register and operable simultaneously with said write counter means connected to said corresponding vector register, for sequentially indicating addresses of storage locations at which a read operation is to be effected for vector elements held by the corresponding vector register when the corresponding vector register is selected by an instruction so as to read the held vector elements.

2. A vector data processor according to claim 1, further comprising:

at least one receive means connected to receive vector elements from any one of said vector registers for sequentially processing vector elements from said vector registers.

3. A vector processor according to claim 2, wherein said control means further includes:

means connected to said plurality of write counter means and said plurality of read counter means and responsive to instructions for enabling said write counter means and said read counter means connected to a selected vector register so as to perform said write operation and said read operation for the selected vector register in an overlapping manner with said sequential read operation being effected after the start of said sequential write operation.

4. A vector data processor according to claim 3, wherein said enabling means includes means for enabling said write counter means and said read counter means connected to the selected vector register to start in response to first and second instructions, respectively.

5. A vector data processor according to claim 3, wherein said enabling means includes means for controlling said plurality of write counter means and said plurality of read counter means so as to sequentially read out a set of vector elements from a first selected vector register, to sequentially provide the vector elements to said operation means as operand vector elements so as to sequentially write into a second selected vector register a set of result vector elements which is a set of vector elements sequentially provided by said operation means as the results of said operation performed on the set of operand vector elements, so as to sequentially read the result vector elements from said second vector register in an overlapping manner with and after start of the writing of the set of result vector elements into said second vector register, and so as to sequentially provide the read out result vector elements to said receive means.

6. A vector data processor according to claim 3, wherein said enabling means includes means connected to said plurality of write counter means and said plurality of read counter means and responsive to a first instruction for enabling read counter means connected to a first vector register selected by the first instruction to perform the read operation for the first vector register and to sequentially provide the read out vector elements to said operation means as operands therefor, responsive to the first instruction for enabling write counter means connected to a second vector register selected by the first instruction to perform said write operation sequentially for result vector elements provided from said operation means as the results of the operation thereby for the operands, and responsive to a second instruction which selects the second vector register for enabling said read counter means connected to said second vector register to perform the read operation for the result vector elements stored in the second vector register, and to provide the read out result vector elements into the second vector register.

7. A vector data processor according to claim 6, wherein said receive means includes adder means for sequentially performing an addition on each of the result vector elements read out from said second vector register and sequentially generating a set of addresses for a set of vector elements stored in said main storage as the results of said addition.

15. A vector data processor according to claim 1, wherein said control means further comprises:

enabling means connected to said plurality of write counter means and said plurality of read counter means and responsive to an instruction requiring reading of vector elements held in one of said vector registers selected by the instruction so as to provide the held vector elements to said main storage or said operation means for enabling said read counter means connected to said selected vector register so as to read the held vector elements, and responsive to an instruction requiring writing of vector elements provided from said main storage or said operation means into one of said vector registers selected by the instruction of enabling said write counter means connected to said one vector register so as to write the provided vector elements into said one vector register.

16. A vector data processor according to claim 15, further comprising:

at least one receive means connected to receive vector elements from any one of said vector registers for sequentially processing vector elements from said vector registers; and

wherein said enabling means includes means connected to said plurality of write counter means and said plurality of read counter means and responsive to a first instruction for enabling read counter means connected to a first vector register selected by the first instruction to perform the read operation for the first vector register and to sequentially provide the read out vector elements to said operation means as operands therefor, responsive to the first instruction for enabling write counter means connected to a second vector register selected by the first instruction to perform said write operation sequentially for result vector elements provided from said operation means as the results of the operation thereby for the operands, and responsive to a second instruction which selects the second vector for enabling said read counter means connected to said second vector register to perform the read operation for the result vector elements stored in the second vector register, and to provide the read out result vector elements to said receive means, wherein said reading of the set of result vector elements from the second vector register for the second instruction is initiated in an overlapping manner with and after start of the writing operation of the result vector elements into the second vector register.

8. A vector data processor, comprising:

storage means for storing plural sets of vector elements;

a plurality of vector registers each having a plurality of addressable memory locations and being connected to said storage means so as to receive vector elements from or provide vector elements to said storage means;

control means connected to said plurality of vector registers and responsive to an instruction for sequentially writing vector elements provided to said plurality of vector registers into plural memory locations of a vector register when the vector register is selected by the instruction to receive the vector elements and responsive to an instruction for sequentially reading vector elements held by a vector register when the vector register is selected by the instruction to provide the held vector elements;

arithmetic means connected to said plurality of vector registers for performing an arithmetic operation on first vector elements read out sequentially from one of said vector registers selected by an instruction which requires execution of the arithmetic operation and for sequentially providing a vector register with vector elements corresponding to the result of the arithmetic operation; and

access means connected to said vector registers and said storage means for performing an operation on second vector elements read out sequentially from one of said vector registers selected by an instruction which requires execution of an access by said access means to provide corresponding to the results of the operation by said access means data signals as a sequence of addresses for said storage means and for sequentially accessing said storage means with the sequence of addresses to fetch and provide third vector elements having the sequence of addresses among the plural sets of vector elements from said storage means to a selected vector register.

9. A vector data processor according to claim 8, wherein the third vector elements comprise vector elements selected from a set of fourth vector elements among the plural sets of vector elements and values of respective second vector elements depend on address differences between the address of the first vector element of the set of fourth vector elements and addresses of respective third vector elements;

and

wherein said access means includes a first register for holding the address of the first vector element of the set of fourth vector elements and operation means connected to said first register for performing an operation on the address of the first vector element of the set of fourth vector elements and each of the second vector elements to provide the resultant data signals as the sequence of the addresses for the fourth vector elements.

10. A vector data processor according to claim 9, wherein the values of respective second vector elements are equal to the address differences;

and

wherein said operation means comprises adder means.

11. A vector data processor according to claim 10, further comprising another access means connected to said storage means for accessing said storage means, including:

second register means for holding an address of the first vector element of fifth vector elements stored in said storage means;

third register means for holding an incremental value representing a difference between the address of two adjacent vector elements of the fifth vector elements;

address means connected to said second and third register means for repeatedly adding the incremental value to the content of the second register means to generate a sequence of addresses of the fifth vector elements and for sequentially accessing said storage means with the generated sequence of the addresses to fetch and provide the fifth vector elements to said vector registers.

12. A vector data processor according to claim 11, wherein said adder means and said address means share a common adder for use in the addition by said adder means and in the addition by said address means.

13. A vector data processor according to claim 8, wherein said control means includes means responsive to a first kind of instruction for sequentially reading vector elements from a vector register selected by the first kind of instruction to provide the read vector elements to said arithmetic means and for writing vector elements provided from the arithmetic means as a result of the operation on the provided vector elements into a vector register selected by the first kind of instruction and responsive to a second kind of instruction for sequentially reading and providing vector elements from a vector register selected by the second kind of instruction to said access means and for writing vector elements fetched by said access means based upon the provided vector elements into a vector register selected by the second kind of instruction.

14. A vector data processor according to claim 8, wherein said control means includes:

a plurality of read counter means each connected to control a respective one of said vector registers for sequentially indicating addresses of storage locations within the vector register controlled thereby at which a read operation is effected;

a plurality of write counter means each connected to control a respective one of said vector registers for sequentially indicating addresses of storage locations within the vector register controlled thereby at which a write operation is effected; and

means connected to said plurality of read counter means and said plurality of write counter means and responsive to an instruction for selectively controlling said read counter means connected to a vector register selected by the instruction to read vector elements therefrom and said write counter means connected to a vector register selected by the instruction to write vector elements therein, said controlling means being capable of controlling said write counter means and said read counter means both connected to the same vector register in such a manner that read operations are started for the vector register before completion of write operations to the vector register so that vector elements provided from said arithmetic means start to be provided to said access means before completion of writing of the vector elements.

17. A vector data processor according to claim 8, said control means includes select means for selectively connecting a vector register selected by an instruction to said access means so that vector elements held by the selected vector register are transferred to said access means.

18. A vector data processor according to claim 8, wherein said control means includes means responsive to an instruction which requires execution of an arithmetic operation by said arithmetic means for sequentially reading vector elements from a vector register selected by the instruction to provide the read vector elements to said arithmetic means and for writing vector elements provided from the arithmetic means as a result of the operation on the provided vector elements into a vector register selected by the instruction and responsive to an instruction which requires execution of the access by said access means for sequentially reading and providing vector elements from a vector register selected by the access instruction to said access means and for writing vector elements fetched by said access means based upon the provided vector elements into a vector register selected by the access instruction.

19. A vector data processor, comprising:

storage means for storing plural sets of vector elements;

a plurality of vector registers each having a plurality of addressable memory locations and being connected to said storage means so as to receive vector elements from or provide vector elements to said storage means;

control means connected to said plurality of vector registers and responsive to an instruction for sequentially writing vector elements provided to said plurality of vector registers into plural memory locations of a vector register when the vector register is selected by the instruction to receive the vector elements and responsive to an instruction for sequentially reading vector elements held by a vector register when the vector register is selected by the instruction to provide the held vector elements;

arithmetic means connected to said plurality of vector registers for performing an arithmetic operation on first vector elements read out sequentially from a first vector register selected by an instruction which requires execution of the operation by said arithmetic means and for sequentially providing a second vector register selected by the instruction which requires the arithmetic operation with vector elements corresponding to the result of the operation so that the vector elements are written into the second vector register; and

access means connected to said vector registers and said storage means for performing an operation on second vector elements read out sequentially from one of said vector registers selected by an instruction which requires execution of an access by said access means to generate a sequence of addresses for third vector elements stored in said storage means and for sequentially accessing said storage means with the generated sequence of addresses to fetch and provide the third vector elements from said storage means to a third vector register selected by the instruction which requires execution of an access so that the third vector elements are written into the third vector register.