Random access memory with high density and low power

• US 4,653,025 A
• Filed: 12/21/1984
• Issued: 03/24/1987
• Est. Priority Date: 12/23/1983
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yatsuda, Yuji, Horiguchi, Masashi, Aoki, Masakazu, Minato, Osamu, Takagi, Katsuaki
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/685,132
• Time in Patent Office: 823 Days
• Field of Search: 365/190, 365/154, 365/156, 365/174, 365/189, 365/230
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A static RAM having a plurality of memory cells. Each memory cell consists of driver MOST'"'"'s that are connected to each other in a crossing manner, and transfer MOST'"'"'s that connect storage nodes of the memory cell to the data lines. The driver MOST'"'"'s are comprised of n-channel MOST'"'"'s, and the transfer MOST'"'"'s are comprised of p-channel MOST'"'"'s.

Claims

1. A semiconductor memory comprising:

a plurality of memory cells each of which is comprised of;

a first n-channel MOST and a second n-channel MOST, each of which is provided in a p-type semiconductor body, the gate of said first n-channel MOST being connected to the drain of said second n-channel type MOST, and the gate of said second n-channel type MOST being connected to the drain of said first n-channel type MOST; and

a first p-channel MOST and a second p-channel MOST, each of which is provided in an n-type semiconductor body, the drain of said first p-channel MOST being coupled to the drain of said first n-channel MOST to constitute a first storage node, and the drain of said second p-channel MOST being coupled to the drain of said second n-channel MOST to constitute a second storage node;

a plurality of first and second data lines each of which is coupled to the source of the first and second p-channel MOSTs in the memory cells;

a plurality of word lines coupled to the gates of the first and second p-channel MOSTs in the memory cells;

a first terminal region provided in said n-type body and coupled to a first power source terminal so as to bias said drains of the p-channel MOSTs in reverse and supply a current in reverse bias ILp to said drains of the p-channel MOSTs; and

a second terminal region provided in said p-type body and coupled to a second power source terminal so as to bias said drains of the n-channel MOSTs in reverse,

wherein said current in reverse bias ILp is greater than a current in reverse bias ILn that flows from said drains of the n-channel MOSTs into said second terminal region.

2. A semiconductor memory according to claim 1, wherein the ratio of mutual conductance of the first and second p-channel MOSTs to mutual conductance of the first and second n-channel MOSTs is set to be about 1:

2.

3. A semiconductor memory according to claim 1, wherein the ratio of channel width/channel length of the first and second p-channel MOSTs to channel width/channel length of the first and second n-channel MOSTs is set to be about 1:

2.

4. A semiconductor memory according to claim 1. further including means to select a word line by lowering the voltage of the word line from a high level to a low level.

5. A semiconductor memory according to claim 1, further comprising a trench region which is provided so as to isolate said p-type body from said n-type body, said trench region having a narrow width but a large depth.

6. A semiconductor memory according to claim 5, wherein an insulating material is provided in said trench region.

7. A semiconductor memory according to claim 5, wherein a conductive material is provided in said insulating material and is set at a certain potential so as to form a depletion layer along said trench in said n-type body.

8. A semiconductor memory according to claim 5, further comprising a p-type region which is provided under the drain of said p-channel MOST along said trench in said n-type body.