Detector array module fabrication process

• US 4,672,737 A
• Filed: 08/02/1985
• Issued: 06/16/1987
• Est. Priority Date: 01/23/1984
• Status: Expired due to Term

• Current Assignee: Irvine Sensors Corp.
• Original Assignee: Irvine Sensors Corp.
• Inventors: Carson, John C., Clark, Stewart A.
• Primary Examiner(s): Weisstuch, Aaron
• Application Number:
  US06/761,889
• Time in Patent Office: 683 Days
• Field of Search: 29/572, 29/576 J, 29/577 R, 29/590, 156/643, 156/630, 204/192 E, 250/578
• US Class Current: 438/59
• CPC Class Codes: H01L 25/042 the devices being arranged next to each other solar cells H01L31/042
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A photo-detector array module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of photo-detectors on the focal plane end, and of thin film circuitry on the back plane end, each plane is etched to cut back the semiconductor material, then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Claims

1. A method for fabricating a photo-detector array module comprising:

providing a number of equal-sized semiconductor chips, each having integrated circuitry thereon, and each having a multiplicity of closely spaced electrical contact points at one end thereof;

stacking and bonding the semiconductor chips to form a rectangular parallelepiped structure with the electrical contact points in an array of closely spaced points on the focal plane end of the stacked chips;

etching the focal plane ends of the stacked chips to remove a small amount of the body material of the chips while leaving the contact points protruding;

depositing insulation material to cover the etched focal plane ends of the stacked chips;

removing sufficient material from the insulation-covered ends of the stacked chips to uncover the electrical contact points; and

placing a multiplicity of photo-detectors on the insulation-covered ends of the stacked chips in such a way that each photo-detector is in electrical contact with a single electrical contact point, while being otherwise insulated from the body material of the semiconductor chips.

2. The photo-detector fabricating array method of claim 1 wherein the step of placing photo-detectors on the stacked chips includes:

depositing a metallic layer on the insulation-covered focal plane ends of the stacked chips;

bonding photo-detector material to the metallic layer with conductive bonding material; and

dividing the photo-detector material and the underlying conductive material into islands which provide individual photo-detectors.

3. The photo-detector array fabricating method of claim 2 wherein the step of etching the ends of the stacked chips is accomplished by a dry process using a gas plasma.

4. The photo-detector array fabricating method of claim 2 wherein each chip in the stack is separated from the adjacent chips by insulating material overlying the integrated circuitry, and the electrical contact points are partially supported by such material during the steps of first etching, and then depositing insulation material on, the focal plane ends of the chips, thereby preventing the protruding contact points from making electrical contact with the chip substrates.

5. The photo-detector array fabricating method of claim 1 wherein the step of etching the ends of the stacked chips includes:

etching back the material used to bond the stack of chips together; and

then etching the ends of the stacked chips to remove a small amount of the body material.

6. The photo-detector array fabricating method of claim 1 wherein the step of etching the ends of the stacked chips is accomplished by a dry process using a gas plasma.

7. The photo-detector array fabricating method of claim 1 wherein each chip in the stack is separated from the adjacent chips by insulating material overlying the integrated circuitry, and the electrical contact points are partially supported by such material during the steps of first etching, and then depositing insulation material on, the focal plane ends of the chips, thereby preventing the protruding contact points from making electrical contact with the chip substrates.

8. A method for fabricating a photo-detector array module comprising:

providing a number of equal-sized semiconductor chips, each having integrated circuitry thereon, and each having a plurality of electrical contact points at one end thereof provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate;

stacking and bonding the semiconductor chips to form a rectangular parallelepiped structure with the electrical contact points on the back plane end of the stacked chips;

etching the back plane end of the stacked chips to remove a small amount of the body material of the chips to leave the contact points protruding;

depositing insulation material on the etched ends of the stacked chips to cover the back plane;

removing sufficient material from the back plane to uncover the electrical contact points;

forming thin film conductors on the back plane to make contact with appropriate electrical contact points thereon, each conductor extending across the end of its contact points to provide a T-shaped junction; and

providing electrical connections leading from the conductors on the back plane to exterior circuitry.

9. The photo-detector array fabricating method of claim 8 wherein the step of providing electrical connections to external circuitry includes:

forming T-shaped thin film junctions over the ends of the conductors on the back plane to provide electrical connections extending perpendicular to the back plane.

10. A method for fabricating a photo-detector array module comprising:

providing a number of equal-sized semiconductor chips, each having a semiconductor substrate with integrated circuitry thereon, and each having a multiplicity of closely spaced electrical contact points at one end thereof provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate;

stacking and bonding the semiconductor chips to form a rectangular parallelepiped structure with the electrical contact points in an array of closely spaced points on the focal plane ends of the stacked chips;

etching the focal plane ends of the stacked chips to remove a small amount of the body material of the chips while leaving the contact points protruding;

depositing insulation material to cover the etched focal plane ends of the stacked chips;

removing sufficient material from the insulation-covered ends of the stacked chips to uncover the electrical contact points; and

placing a multiplicity of photo-detectors on the insulation-covered ends of the stacked chips in such a way that each photo-detector is in electrical contact with a single electrical contact point, while being otherwise insulated from the body material of the semiconductor chips.

11. The photo-detector array fabricating method of claim 10 wherein the step of etching the ends of the stacked chips is accomplished by a dry process using a gas plasma.

12. The photo-detector array fabricating method of claim 10 wherein each chip in the stack is separated from the adjacent chips by insulating material overlying the integrated circuitry, and the electrical contact points are partially supported by such material during the steps of first etching, and then depositing insulation material on, the focal plane ends of the chips, thereby preventing the protruding contact points from making electrical contact with the chip substrates.

13. A method for fabricating an electro-optical array module comprising:

providing a number of equal-sized semiconductor chips, each having integrated circuitry thereon, and each having a multiplicity of closely spaced electrical contact points at one end thereof;

stacking and bonding the semiconductor chips to form a rectangular parallelepiped structure with the electrical contact points in an array of closely spaced points on a planar surface formed by the ends of the stacked chips;

etching the planar-surface-forming ends of the stacked chips to remove a small amount of the body material of the chips while leaving the contact points protruding;

depositing insulation material to cover the etched ends of the stacked chips; and

removing sufficient material from the insulation-covered ends of the stacked chips to uncover the electrical contact points.

14. The module fabricating method of claim 13 wherein the step of etching the ends of the stacked chips is accomplished by a dry process using a gas plasma.

15. The module fabricating method of claim 13 wherein each chip in the stack is separated from the adjacent chips by insulating material overlying the integrated circuitry, and the electrical contact points are partially supported by such material during the steps of first etching, and then depositing insulation material on, the planar-surface-forming ends of the chips, thereby preventing the protruding contact points from making electrical contact with the chip substrates.