Charge depletion meter
First Claim
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1. A charge depletion meter apparatus comprising in combination:
- a sensing means connected to a battery source to sense the amount of charge flowing therethrough, said sensing means providing a charge signal,a current to frequency converter means coupled to said sensing means to receive said charge signal therefrom, said current to frequency converter means converting said charge signal to a digital signal which is representative thereof,a divider means coupled to said current to frequency converter means to receive said digital signal therefrom, said divider means dividing said digital signal by a predetermined number, said divider means providing an output pulse signal,a decimal counter means coupled to said divider means to receive said output pulse signal, said decimal counter means accumulating said output pulse signal,reset means coupled respectively to said divider means and said decimal counter means for manually resetting both to zero, and,a display means coupled to said decimal counter means to receive said output pulse signal therefrom, said display means displaying said output pulse signal.
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Abstract
A charge depletion meter apparatus having a current to frequency converter to sense and convert the current drain of a battery source to a digital signal which is divided and then accumulated in a counter. An LCD display unit displays the accumulated charge which is received from the counter.
21 Citations
6 Claims
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1. A charge depletion meter apparatus comprising in combination:
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a sensing means connected to a battery source to sense the amount of charge flowing therethrough, said sensing means providing a charge signal, a current to frequency converter means coupled to said sensing means to receive said charge signal therefrom, said current to frequency converter means converting said charge signal to a digital signal which is representative thereof, a divider means coupled to said current to frequency converter means to receive said digital signal therefrom, said divider means dividing said digital signal by a predetermined number, said divider means providing an output pulse signal, a decimal counter means coupled to said divider means to receive said output pulse signal, said decimal counter means accumulating said output pulse signal, reset means coupled respectively to said divider means and said decimal counter means for manually resetting both to zero, and, a display means coupled to said decimal counter means to receive said output pulse signal therefrom, said display means displaying said output pulse signal. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification
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Current AssigneeUnited States Of America As Represented By The Secretary Of The Air Force
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Original AssigneeUnited States Of America As Represented By The Secretary Of The Air Force
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InventorsSchneider, Josef F.
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Primary Examiner(s)Eisenzopf, Reinhard J.
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Assistant Examiner(s)Mueller, Robert W.
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Application NumberUS06/675,174Time in Patent Office952 DaysField of Search324/427, 324/426, 324/428, 320/48, 320/48 X, 340/636US Class Current324/427CPC Class CodesG01R 31/36 Arrangements for testing, m...
