Circuit for recovering the carrier wave in digital transmission systems

• US 4,687,999 A
• Filed: 04/23/1986
• Issued: 08/18/1987
• Est. Priority Date: 04/30/1985
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Desperben, Lydie, Sari, Hikmet, Moridi, Said
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Pascal, Robert J.
• Application Number:
  US06/855,527
• Time in Patent Office: 482 Days
• Field of Search: 329/104, 329/109, 329/110, 329/112, 329/122, 329/124, 329/146, 375/39, 375/120, 455/214
• US Class Current: 331/23
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop

Abstract

A circuit for recovering the carrier of a digitally modulated wave having a phase symmetry 2π/M, wherein M is the order of the symmetry, includes means for automatic and fast acquisition comprising a voltage-controlled oscillator having an output supplying said carrier and a control input to which an error signal ε(φ) is applied in order to change the oscillator phase and to adjust it to the phase of the digital modulated wave. This wave is introduced in two channels, one being in phase and the other being in quadrature with the carrier, each comprising the series arrangement of: a demodulator, a low-pass filter, reconstruction means for reconstructing a signal and for determining the error between the filtered and reconstructed signals, the quadrature channel comprising in addition a 90° phase shifter, the two channels being joined together with the aid of a phase comparator arrangement which produces a comparison signal and a variable-rate sampling clock. With the representation of the signals from the in-phase and quadrature channels defining the states of a signal constellation of the modulated wave, the phase comparator arrangement comprises means for selecting received signal points with the aid of zones which are centered on or eccentric to certain diagonal states of the signal constellation, and means for generating the sampling clock by eliminating from a recovered symbol clock an active edge capable of validating zero crossings of the comparator signal which do not correspond to a phase difference equal to 2kπ/M (k and M integers).

Claims

1. A circuit for recovering the carrier of a digitally modulated wave, said digitally modulated wave having a phase symmetry 2π

/M, where M is the symmetry order, comprising;

(a) means for fast automatic acquisition, including;

(i) a voltage-controlled oscillator, having an output at which said carrier is provided, and having a control input for receiving an error signal ε

(φ

), said oscillator changing phase in response to said error signal ε

(φ

)

(ii) a first channel, coupled to receive said digitally modulated wave, said first channel including the following elements in series;

(A) a demodulator producing an in-phase demodulated signal X₁, said demodulator being coupled to receive said digitally modulated wave and said output carrier of said oscillator;

(B) a low-pass filter, coupled to receive said demodulated signal X₁, and producing therefrom a filtered signal X; and

(C) means for determining an error e_x, said means for determining including;

(I) means for producing a reconstructed signal X from said filtered signal X; and

(II) means for combining said reconstructed signal X and said filtered signal X to derive said error e_x =X-X;

(iii) a second channel, coupled to receive said digitally modulated wave, said second channel including the following elements in series;

(A) a phase shifter for shifting the output carrier of said oscillator by 90°

;

(B) a demodulator receiving said digitally modulated wave and receiving an output signal from said phase shifter and producing therefrom a quadrature phase demodulated signal Y₁ ;

(C) a low-pass filter coupled to receive said demodulated signal Y₁, and producing therefrom a filtered signal Y; and

(D) means for determining an error e_y, said means for determining including;

(I) means for producing a reconstructed signal Y from said filtered signal Y; and

(II) means for combining said reconstructed signal Y and said filtered signal Y to derive said error e_y =Y-Y;

(iv) a phase comparator coupled to receive said error e_x, said error e_y, said filtered signal X, said filtered signal Y, and a basic clock H which corresponds to a recovered symbol clock, said phase comparator producing a comparator signal S and a variable rate sampling clock which reproduces the basic clock H by eliminating certain edges, signal points being defined in said phase comparator on an imaginary plane which has an origin and orthogonal real and imaginary axes, said signal points being defined by pairs of in-phase and quadrature-phase values, idealized ones of said signal points being states of a signal constellation, which signal constellation represents said digitally modulated wave;

(v) a bistable trigger controlled by said sampling clock and coupled to receive said comparator signal S; and

(vi) an amplifying filter for producing the error signal ε

(φ

) from an output of said bistable trigger;

(b) wherein the improvement comprises that said phase comparator includes;

(i) means for identifying some of said signal points using selection zones within said imaginary plane, said selection zones representing permissible in-phase and quadrature-phase limits for signal points which correspond to certain ones of a plurality of diagonal states, said diagonal states being those states of said signal constellation which have in-phase and quadrature phase values of equal absolute value, said selection zones being defined so that;

(A) none of at least one imaginary circle in said imaginary plane intersects said selection zones, each said imaginary circle being defined so that its center is at the origin of said imaginary plane and its circumference contains at least one said state of said signal constellation which is not a diagonal state; and

(B) said selection zones do not contain the axes of said imaginary plane;

(ii) means for generating said sampling clock by eliminating from said basic clock H all active edges capable of validating in said bistable trigger zero crossings of said comparator signal S which do not correspond to a phase difference equal to 2kπ

/M, where k is an integer.

2. The circuit of claim 1 wherein said means for identifying compares the in-phase and quadrature-phase values of said signal points with respective predetermined thresholds.

3. The circuit of claim 2 wherein the predetermined thresholds are determined such that a difference between the phases of signal points within each selection zone and the phase of the diagonal state within the selection zone has an absolute value less than a predetermined value, except at 2kπ

/M.

4. The circuit of claim 1, 2, or 3 wherein the means for identifying and the means for generating comprise:

(a) in the first channel;

(i) two amplitude comparators comparing the error e_x =X-X to respective thresholds a and -a and producing respective signals M_x and N_x at a first logic value when the error e_x exceeds a or is less than -a, respectively;

(ii) three amplitude comparators comparing the signal X to respective thresholds 0,2 and -2 and producing respective signals Q_x, R_x and T_x at the first logic value when the signal X exceeds the thresholds for the first or second comparators or is less than the threshold for the third comparator, respectively;

(iii) a first selection circuit producing a signal P_x such that P_x =N_x ·

M_x ; and

(iv) a second selection circuit producing a signal A_x such that A_x =R_x ·

Q_x +T_x ·

Q_x ;

where the symbol (·

) represents the logic AND function and the symbol (+) represents the logic OR function;

(b) in the second channel;

(i) two amplitude comparators comparing the error e_y =Y=Y to respective thresholds a and -a and producing respective signals M_y and N_y at the first logic value when the error e_y exceeds a or is less than -a, respectively;

(ii) three amplitude comparators comparing the signal Y to respective thresholds 0, 2 and -2, and producing respective signals Q_y, R_y and T_y at the first logic value when the signal Y exceeds thresholds for the first or second comparators or is less than the threshold for the third comparator, respectively;

(iii) a third selection circuit producing a signal P_y such that P_y =N_y ·

M_y ; and

(iv) a fourth selection circuit producing a signal A_y such that A_y =R_y ·

Q_y +T_y ·

Q_y ;

(c) an exclusive NOR circuit receiving the signals A_x and A_y at its inputs;

(d) a first AND-circuit receiving the output of the exclusive-NOR circuit and the signals P_x and P_y, for producing a signal P_z ; and

(e) a second AND-circuit receiving the signal P_z and the basic clock H for producing the sampling clock.

5. The circuit of claim 1, 2, or 3 wherein the means for identifying and the means for generating comprise:

(a) in the first channel;

(i) two amplitude comparators comparing the error e_x =X-X to respective thresholds a and -a and producing respective signals M_x and N_x at a first logic value when the error e_x exceeds a or is less than -a, respectively;

(ii) three amplitude comparators comparing the signal X to respective thresholds 0, 2 and -2 and producing respective signals Q_x, R_x and T_x at the first logic value when the signal X exceeds the thresholds for the first or second comparators or is less than the threshold for the third comparator, respectively;

(iii) a first selection circuit producing a signal P_x such that P_x =N_x ·

Q_x +M_x ·

Q_x ; and

(iv) second selection circuit producing a signal A_x such that A_x =R_x ·

Q_x +T_x ·

Q_x ;

where the symbol (·

) represents the logic AND function and the symbol (+) represents the logic OR function;

(b) in the second channel;

(i) two amplitude comparators comparing the error e_y =Y-Y to respective thresholds a and -a and producing respective signals M_y and N_y at the first logic value when the error e_y exceeds a or is less than -a, respectively;

(ii) three amplitude comparators comparing the signal Y to respective thresholds 0, 2 and -2 and producing respective signals Q_y, R_y and T_y at the first logic value when the signal Y exceeds the thresholds for the first or second comparators or is less than the threshold for the third comparator, respectively;

(iii) a third selection circuit producing a signal P_y such that P_y =N_y ·

Q_y +M_y ·

Q_y ; and

(iv) a fourth selection circuit producing a signal A_y such that A_y =R_y ·

Q_y +T_y ·

Q_y ;

(c) an exclusive NOR-circuit receiving the signals A_x and A_y at its input;

(d) a first AND-circuit receiving the output of the exclusive NOR-circuit and the signals P_x and P_y, and producing a signal P_z ; and

(e) a second AND-circuit receiving the signal P_z and the basic clock H for producing the sampling clock.