Multiple range interval clutter cancellation circuit

• US 4,688,044 A
• Filed: 07/07/1986
• Issued: 08/18/1987
• Est. Priority Date: 07/07/1986
• Status: Expired due to Term

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: O'Brien, Edwin L.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Hayes, Jr., Donald E.
• Application Number:
  US06/882,582
• Time in Patent Office: 407 Days
• Field of Search: 342/159, 342/160, 342/161, 342/162, 342/163, 342/164
• US Class Current: 342/160
• CPC Class Codes: G01S 13/20 whereby multiple time-around echoes are used or eliminated
• CPC Class Codes: G01S 13/526 performing filtering on the whole spectrum without loss of range information, e.g. using delay line cancellers or comb filters G01S13/5244 takes precedence
• CPC Class Codes: G01S 13/53 performing filtering on a single spectral line and associated with one or more range gates with a phase detector or a frequency mixer to extract the Doppler information, e.g. pulse Doppler radar G01S13/5244 takes precedence

Abstract

A multiple range interval clutter cancellation circuit for MTI radars is disclosed, for assuring cancellation of narrow band clutter in the second or further range interval, while preserving wideband cancellation in the nearer range intervals and economizing on the number of fill pulses. The circuit includes two clutter cancellers. One canceller has a relatively narrow band clutter rejection bandwidth, and effectively a higher number of fill pulses in relation to the clutter rejection bandwidth and effective number of fill pulses for the second canceller. The outputs of the two cancellers are subjected to an AND gate function, such that only targets which pass through the clutter rejection bandwidth of both cancellers are reported as a target. The circuit obtains the elimination of returns from ambiguous range interval clutter with less transmitted energy and time than conventional canceller circuits.

Claims

1. A Moving Target Indicator (MTI) radar processor for processing the radar return signals resulting from n radar pulses transmitted at a constant pulse repetition rate (PRF) to detect moving targets while rejecting clutter in a second range interval;

comprising;

a first clutter canceller circuit arranged to process radar return signals received during the n inter-pulse-period (IPP) intervals following the first pulse and to provide a first canceller output signal during the nth such interval;

a second clutter canceller circuit arranged to process radar return signals received during said nth interval and the n-2 immediately preceding intervals and to provide a second canceller output signal during said nth IPP interval;

whereby the first and second canceller circuits provide respective clutter rejection null responses, with the first canceller circuit having increased degrees of freedom for the tailoring of the respective null response in relation to the null response of the second canceller circuit; and

an output processor for processing said first and second canceller circuit output signals and reporting as moving targets only those targets which pass through the clutter rejection nulls of both the first and second canceller circuits, whereby said processor provides the capability of the clutter rejection null response of the first canceller circuit in the first range interval and the capability of the clutter rejection null response of the second canceller circuit in the second range interval.

2. The radar processor of claim 1 wherein said first and second canceller output signals comprise binary-level signals wherein a low state is indicative of the "no target detected" condition and a high state is indicative of the "target detected" condition, and wherein said output processor comprises an AND gate device for performing a logical AND function on said first and second canceller output signals, thereby providing a high output signal indicative of the "target detected" condition if and only if both canceller output signals are at said high state.

3. The radar processor of claim 2 wherein said first canceller circuit comprises a double canceller circuit having a relatively broad clutter rejection null response and said second canceller circuit comprises a single canceller circuit having a relatively narrow clutter rejection null response, and wherein the processor provides the capability of the relatively broad band clutter rejection null of the first canceller circuit in the first range interval and the capability of the narrower band clutter rejection null of the second canceller circuit in the second range interval.

4. A Moving Target Indicator (MTI) radar processor for processing radar return signals from radar pulses transmitted at a fixed pulse repetition frequency (PRF), comprising:

a first MTI clutter canceller circuit requiring n transmitted pulses to provide a first clutter rejection bandwidth over the first range interval and arranged to provide a first MTI circuit output indicative of a particular target detection condition, including the "no target detected" and "target detected" conditions, during the 1/PRF interval following the nth transmitted pulse;

a second MTI clutter canceller circuit requiring n-m transmitted pulses to provide a second clutter rejection bandwidth over the first through the (m+1)th range intervals and arranged to provide a second MTI circuit output indicative of a particular target detection condition, including the "no target detected" and "target detected" conditions; and

means for performing a logical "AND" function on said first and second MTI circuit outputs and providing a processor output, such that only targets which are passed through each of said first and second clutter rejection bandwidths and reported as "target present" conditions by both canceller circuits indicate the radar processor "target detected" condition;

whereby said radar processor achieves the wider-band clutter rejection capability of the first canceller circuit for first range interval clutter and the narrower-band clutter rejection capability of the second canceller circuit for up to the (m+1)th range interval clutter while requiring only n transmitted pulses.

5. The radar processor of claim 4 wherein the index value m equals one, and the (m+1)th range interval is the second range interval.

6. The radar processor of claim 5 wherein said first canceller circuit comprises a double canceller circuit and said second canceller circuit comprises a single canceller circuit.

7. A Moving Target Indicator (MTI) radar processor for processing the radar return signals resulting from n radar pulses transmitted at a constant pulse repetition rate (PRF) and detecting moving targets while rejecting clutter in the second range interval with fewer transmitted fill pulses:

a first canceller circuit for receiving said radar return signals, said circuit comprising an n-tap transversal filter means for providing a first clutter cancellation null response, the respective taps being coupled by respective delay devices for providing a 1/PRF delay, means for weighting the signals at the respective taps in accordance with n respective weights and means for summing the respective weighted tap signals during the 1/PRF time interval following the nth transmitted pulse to provide a first canceller output indicative of a particular target detection condition, including the "target detected" condition and of the "no target detected" condition;

a second canceller circuit for receiving said radar returns, said circuit comprising an n-1 tap transversal filter means for providing a second clutter cancellation null response, the respective taps being coupled by respective 1/PRF delay device means, means for weighting the signals at the respective taps in accordance with n-1 respective weights and summing the respective weighted tap signals during said 1/PRF time interval to provide a second canceller output indicative of a particular target detection condition, including the "target detected" and "no target detected" conditions;

wherein said n-tap filter means of said first canceller circuit provides increased degrees of freedom for defining said first null response over the degrees of freedom provided by said n-1 tap filter means of said second filter means in defining said second null response; and

"AND" circuit for processing said first and second output signals and providing a radar processor output signal during said 1/PRF interval indicative of a radar "target detected" condition only if each of said first and second canceller output signals also indicates the "target detected" condition;

whereby said radar processor provides the clutter rejection response of the first canceller for first range interval clutter and the clutter rejection response of the second canceller circuit for second range interval clutter while requiring only n transmitted pulses.

8. A multiple range interval cancellation circuit for Moving Target Indicator (MTI) radars employing a plurality of radar pulses transmitted at a constant pulse repetition rate (PRF), comprising:

a first clutter canceller comprising an n-tap doppler filter set and target detection circuitry for providing a first canceller signal indicative of a particular target detection condition, including the "no target detected" or "target detected" conditions, within one of the range interval cells corresponding to one of said doppler filters, said n-tap doppler filters providing respective first clutter rejection null response;

a second clutter canceller comprising an n-1 tap filter set and target detection circuitry for providing a second canceller circuit indicative of a particular target detection condition, including the "no target detected" or "target detected" conditions, within one of the range interval cells corresponding to one of said doppler filters, said n-1 tap doppler filters providing respective second clutter rejection null responses; and

output circuit means for processing said first and second output signals to provide a processor output signal indicative of the processor "target detected" condition only if each of said first and second canceller output signals also indicate the "target detected" condition.

9. The radar processor of claim 8 wherein said first and second canceller output signals are binary-leveled signals wherein the low state represents the "no target detected" condition and the high state represents the "target detected" condition, and wherein said output circuit means comprises an AND logic gate.