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Apparatus for recording the speed of a vehicle

  • US 4,692,882 A
  • Filed: 12/19/1984
  • Issued: 09/08/1987
  • Est. Priority Date: 04/27/1983
  • Status: Expired due to Fees
First Claim
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1. A digital vehicle speed recorder for recording successive speed values of a motor vehicle over a predetermined road distance, comprising:

  • a pulse generator connected to a velocity sensor in the vehicle for generating control pulses with a pulse separation corresponding to a given road length, a clock generator for generating internal clock pulses, a microcomputer for calculating said speed values on the basis of said control pulses and said clock pulses, a speed value memory for storing successive speed values with a recording rate dependent on the road distance covered, and read-out means associated with said memory for connection with a reproducing instrument for obtaining a visual presentation of the speed values stored in the memory, said microcomputer having a first interrupt input connected to said pulse generator, said microcomputer including in its working memory a counter connected to said clock generator to be incremented by said clock pulses, a memory location for storing a predetermined maximum of the counter value, and comparator means connected to said counter and said memory location for continuously comparing the actual counter value in said counter with said maximum counter value and generating an internal interrupt signal when said counter value exceeds said maximum counter value, said counter and said memory location both being connected to said speed value memory to transfer, in response to each pulse supplied from said pulse generator to said first interrupt input or in response to said internal interrupt signal, whichever occurs first, said actual counter value or said maximum counter value, respectively, or a speed value derived therefrom to said speed value memory,said speed value memory comprising a plurality of memory blocks coupled in series and each having a number of memory locations connected in a circular arrangement, said locations being individually addressed from addressing means in the working memory of said microcomputer in a cyclically repeated order of succession, said memory locations in each block except the last block being grouped in a number of memory sections such that;

    a first memory block is addressed from said addressing means in response to each interrupt signal at said first interrupt input or said internal interrupt, whichever occurs first, for successively recording said counter values or said maximum, respectively, or speed values derived therefrom in the memory locations of the first memory block,all memory blocks except the last one are controlled by said addressing means to address all memory locations of the memory section containing the latest addressed memory location for transferring the speed values in said memory locations to an arithmetic-logic unit of said microcomputer in response to addressing of a predetermined one of said memory locations for calculating a single function value on the basis of all the speed values stored in said memory locations, andthe memory locations of each memory block after the first block are successively addressed by said addressing means for recording function values calculated from the speed values stored in memory sections in the preceding memory block.

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