Hardware logic simulator

• US 4,697,241 A
• Filed: 03/01/1985
• Issued: 09/29/1987
• Est. Priority Date: 03/01/1985
• Status: Expired due to Term

• Current Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Original Assignee: Simulog, Inc.
• Inventors: Lavi, Yoav
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): Juffernbruch, Daniel W.
• Application Number:
  US06/707,040
• Time in Patent Office: 942 Days
• Field of Search: 364/488, 364/489, 364/490, 364/716, 364/200 MS File, 364/900 MS File, 364/800, 364/801, 364/802, 364/578, 307/465, 307/468, 307/469, 307/243, 307/466, 307/467, 434/118, 371/23
• US Class Current: 703/15
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprises a plurality of hardware gates, each of which is programmable so as to correspond to and emulate an element in said logic circuit. Each hardware gate has an output and at least two inputs. A selectively operable interconnection system is provided for establishing a connection between the output of any hardware gate and an input of any hardware gate. A multiplexing system is also provided for operating the interconnection system and determining which, and when, each connection is made between the output of any hardware gate and an input of any hardware gate.

Claims

1. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:

(a) a plurality of harware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs;

(b) interconnnection means selectively operable for establishing a connection between the output of a given hardware gate and an input of any other hardware gate including said given gate; and

(c) multiplex means for operating said interconnection means and determining which, and when, each connection is made.

2. Apparatus according to claim 1 wherein each hardware gate is programmable for emulating an AND gate, an OR gate, a NAND gate, or a NOR gate.

3. Apparatus according to claim 1 wherein each hardware gate comprises a plurality of logic gates interconnected by switches whose setting configures the hardware gate to emulate a logic element in said logic circuit.

4. Apparatus according to claim 3 including means for selectively setting said switches.

5. Apparatus according to claim 3 wherein each hardware gate comprises an AND gate, an OR gate, an inverter, and electronic switches for effecting interconnections between the various gates.

6. Apparatus according to claim 5 including means to operate said switches for programming each hardware gate to emulate a logic element.

7. Apparatus according to claim 6 including means to latch the output of each hardware gate.

8. Apparatus according to claim 1 wherein said multiplex means establishes the output to, and input of, the apparatus and is constructed and arranged to establish temporarily limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto.

9. Apparatus according to claim 8 wherein said multiplex means includes a time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made.

10. Apparatus according to claim 9 wherein said interconnection means includes an input selector associated with the inputs of each hardware gate, and an input bus having a plurality of input bus lines, said input selector being constructed and arranged for selectively connecting the input of a hardware gate to, or selectively disconnecting the input from, any one of said input bus lines of said input bus.

11. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:

(a) a plurality of hardware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs;

(b) interconnection means selectively operable for establishing a connection between the output of any hardware gate and the input of any hardware gate; and

(c) multiplex means for operating said interconnection means and determining which, and when, each interconnection is made;

(d) said multiplex means establishing the output to, and the input of the apparatus, said multiplex means being constructed and arranged to establish temporarily limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto;

(e) said multiplex means including as time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made;

(f) said interconnection means including an input selector associated with the inputs of each hardware gate, and an input bus having a plurality of input bus lines, said input selector being constructed and arranged for selectively connecting the input of a hardware gate to, or selectively disconnecting the input from, any one of said input bus lines of said input bus; and

(g) wherein the number of input lines is equal to the number of output lines.

12. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:

(a) a plurality of hardware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs;

(b) interconnection means selectively operable for establishing a connection between the output of any hardware gate and the input of any hardware gate; and

(c) multiplex means for operating said interconnection means and determining which, and when, each interconnection is made;

(d) said multiplex means establishing the output to, and the input of the apparatus, said multiplex means being constructed and arranged to establish temporally limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto;

(e) said multiplex means including as time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made;

(f) said interconnection means including an input selector associated with the inputs of each hardware gate, and an input bus having a plurality of input bus lines, said input selector being constructed and arranged for selectively connecting the input of a hardware gate to, or selectively disconnecting the input from, any one of said input bus lines of said input bus; and

(g) wherein said input selector includes, for each input to a hardware gate, selectively operable means by which such input can be connected to or disconnected from an input bus line.

13. Apparatus according to claim 12 wherein said selectively operable means includes a first circuit that controls which input bus line is to be connected to and input to a hardware gate, and a second circuit that controls when, and for how long, an input bus line is to be connected to a hardware gate.

14. Apparatus according to claim 13 wherein each of said first and second circuits includes a pass transistor.

15. Apparatus according to claim 14 wherein said input selector includes a comparator/decoder for producing a signal upon the occurrence of a preselected time slot, said second circuit being responsive to a signal to produce by said comparator/decoder for connecting an input bus line to an input of a hardware gate during a preselected time slot.

16. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:

(a) a plurality of hardware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs;

(b) interconnection means selectively operable for establishing a connection between the output of any hardware gate and the input of any hardware gate; and

(c) multiplex means for operating said interconnection means and determining which, and when, each interconnection is made;

(d) said multiplex means establishing the output to, and the input of the apparatus, said multiplex means being constructed and arranged to establish temporally limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto;

(e) said multiplex means including as time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made; and

(f) wherein said interconnection means includes an output distributor associated with with the output of each hardware gate, and an output bus having a plurality of output lines, said output distributor being constructed an arranged for selectively connecting the output of a hardware gate to, or selectively disconnecting the output from, any one of said lines of said output bus.

17. Apparatus according to claim 16 wherein said output distributor includes, for each output from a hardware gate, selectively operable means by which each output can be connected to, or disconnected from, an output bus line.

18. Apparatus according to claim 17 wherein said selectively operable means includes a first circuit that controls which output bus lines is to be connected to an output line from a hardware gate, and a second circuit that controls when, and for how long, an output bus line is to be connected to an output from a hardware gate.

19. Apparatus according to claim 18 wherein each of said first and second circuits includes a pass transistor.

20. Apparatus according to claim 18 wherein said output distributor includes a comparator/decoder for producing a signal upon the occurrence of a preselected time slot, said second circuit being responsive to a signal produced by said comparator/decoder for connecting an output bus line to an output line of a hardware gate during a preselected time slot.

21. Apparatus according to claim 16 wherein an internal enable line and an internal enable circuit for operating the same are associated with each output bus line, said internal enable circuit being selectively operable for establishing the state of said internal enable line.

22. Apparatus according to claim 16 wherein said output bus includes, for each output bus line, an external enable line and an external enable circuit selectively operable for establishing the state of said external enable line.

23. Apparatus according to claim 22 wherein an internal enable line and an internal enable circuit for operating the same are associated with each output bus line, said internal enable circuit being selectively operable for establishing the state of said internal enable line.

24. Apparatus according to claim 23 wherein said selectively operable means includes a first circuit that controls which output bus line is to be connected to an output line from a hardware gate, and a second circuit that controls when, and for how long, an output bus line is to be connected to an output from a hardware gate.

25. Apparatus according to claim 24 wherein said output distributor includes a comparator/decoder for producing a signal upon the occurrence of a preselected time slot, said second circuit being responsive to a signal produced by said comparator/decoder for connecting an output bus line to an output line of a hardware gate during a preselected time slot.

26. Apparatus according to claim 23 wherein said interconnection means includes an input selector associated with the inputs of each hardware gate, and an input bus having a plurality of input bus lines, said input selector being constructed and arranged for selectively connecting the input of a hardware gate to, or selectively disconnecting the input from, any one of said input bus lines of said input bus.

27. Apparatus according to claim 26 wherein said interconnection means includes an input/output (I/O) buffer interposed between said input and output bus lines for selectively connecting an output bus line to a corresponding input bus line.

28. Apparatus according to claim 27 wherein said I/O buffer includes means responsive to the state of an internal enable line associated with a given output bus lines for connecting the latter to the corresponding input bus line.

29. Apparatus according to claim 28 wherein said means responsive to the state of an internal enable line includes a first gated amplifier connecting said given output bus line to its corresponding input bus line, the conduction of said first gated amplifier being controlled by the output of an OR-gate to which said internal enable line is connected.

30. Apparatus according to claim 29 wherein said I/O buffer includes an external bus line associated with corresponding output and input bus lines, and means responsive to the state of an external enable line associated with a given output bus line for connecting the latter to its associated external bus line.

31. Apparatus according to claim 30 wherein said means responsive to the state of an external enable line includes a second gated amplifier connecting an external bus line to its associated output bus line, the conduction of said second gated amplifier being controlled by the state of the external enable line associated with the last mentioned output bus line.

32. Apparatus according to claim 31 wherein the output enable line associated with a given output bus line provides an input to the OR-gate whose output controls the first gated amplifier which said given output line is connected to a corresponding input bus line.

33. Apparatus according to claim 31 wherein a third gated amplifier is connected between the outputs of the first and second gated amplifiers for establishing a connection between an external bus line and the input bus line associated therewith when said third gated amplifier conducts, and a logic element for controlling conduction of said third gated amplifier in response to the state of both the output and internal enable lines associated with the output bus line with which the last mentioned input bus line is associated.

34. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:

(a) a plurality of level 0 modules each of which comprises a plurality of hardware gates having inputs and outputs and individually corresponding to and emulating different logic elements of said logic circuit;

(b) a level 0 output bus having a plurality of output bus lines that correspond to a plurality of input bus lines of a level 0 input bus;

(c) an output distributor associated with each hardware gate for establishing connections between the outputs of the hardware gates and the output bus line of the level 0 output bus;

(d) an input selector associated with each hardware gate for establishing connections between inputs to the hardware gates and the input bus lines of the level 0 input bus; and

(e) an input/output buffer for selectively connecting output bus lines of a level 0 output bus to corresponding input bus lines of the level 0 input bus.

35. Apparatus according to claim 34 including a level 1 bus for interconnecting the input/output buffers of pairs of level 0 modules.

36. Apparatus according to claim 35 including a bus interface connected to each level 1 bus, and a level 2 bus for interconnecting pairs of bus interfaces.

37. Apparatus according to claim 34 including a level 3 bus, and a bus interface connected between a level 2 bus and the level 3 bus.

38. Apparatus according to claim 37 including a level 4 bus, and a bus interface connected between the level 3 bus and the level 4 bus.

39. Apparatus according to claim 38 including a level 5 bus, and a bus interface connected between the level 4 bus and the level 5 bus.