Semiconductor integrated circuit device and method of producing the same

• US 4,701,349 A
• Filed: 12/09/1985
• Issued: 10/20/1987
• Est. Priority Date: 12/10/1984
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Koyanagi, Mitsumasa, Kaneko, Hiroko
• Primary Examiner(s): SMITH, JOHN DOUGLAS
• Application Number:
  US06/806,342
• Time in Patent Office: 680 Days
• Field of Search: 427/93, 427/88, 148/6.3, 156/664
• US Class Current: 438/655
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/3211 Nitridation of silicon-containing layers
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941

Abstract

A silicide layer of a refractory metal for reducing resistance and a nitride layer for preventing diffusion of aluminum are formed on the source and drain regions of an MISFET. The silicide layer is formed in self-alignment with the source and drain regions by two annealings effected at a low temperature and at a high temperature, respectively, and has a low resistance. The nitride layer is formed by directly nitriding the silicide layer.

Claims

1. A method of producing a semiconductor integrated circuit device comprising the steps of:

exposing a part of a surface of silicon on a semiconductor substrate in such a manner that the surface shape of the exposed silicon region is defined by an insulating film;

depositing a refractory metal at least on said exposed silicon region;

forming a silicide layer of said refractory metal on said exposed silicon region, said silicide layer being formed by first annealing below 600°

C. which lets said silicon react with said refractory metal, and having a relatively high resistance;

removing said refractory metal other than the one that has contributed to said silicide layer, whereby said silicide layer remains unremoved; and

effecting a second annealing, in order to change said silicide layer having a relatively high resistance to a silicide layer having a low resistance, said second annealing including an annealing above 900°

C. in a nitrogen atmosphere.

2. A method of producing a semiconductor integrated circuit device according to claim 1 wherein said refractory metal is titanium.

3. A method of producing a semiconductor integrated circuit device according to claim 2 wherein said titanium silicide layer after said first and second annealings is comprised principally of TiSi and TiSi₂, respectively.

4. A method of producing a semiconductor integrated circuit device according to claim 1 wherein said exposed silicon region is a part of said source and/or drain region of said MISFET, and said insulating film defining the surface shape of said exposed silicon region comprises side wall spacers formed on the side walls of said gate electrode of said MISFET and a thick insulating film formed on said semiconductor substrate in such a manner as to encompass said MISFET.

5. A method of producing a semiconductor integrated circuit device according to claim 1 wherein said second annealing is performed so as to change the surface layer of said silicide layer to a nitride layer.

6. A method of producing a semiconductor integrated circuit device according to claim 5 wherein said nitride layer comprises TiN.

7. A method of producing a semiconductor integrated circuit device according to claim 6 wherein lamp annealing is used as said second annealing.

8. A method of producing a semiconductor integrated circuit device according to claim 1 wherein said silicide layer is formed in self-alignment with the exposed silicon region.

9. A method of producing a semiconductor integrated circuit device according to claim 1 wherein the first annealing is performed in a nitrogen or argon atmosphere.

10. A method of producing a semiconductor integrated circuit device according to claim 9 wherein said removing said refractory metal other than the one that has contributed to said silicide layer comprises etching said refractory metal in an etching solution comprising hydrogen peroxide.

11. A method of producing a semiconductor integrated circuit device according to claim 10 wherein, prior to said second annealing, a low temperature heat treatment, at a temperature below 200°

C., is performed to purge the apparatus of oxygen, so as to avoid oxidation of the silicide layer during the second annealing.

12. A method of producing a semiconductor integrated circuit device according to claim 1 wherein said removing said refractory metal other than the one that has contributed to said silicide layer comprises etching said refractory metal in an etching solution comprising hydrogen peroxide.

13. A method of producing a semiconductor integrated circuit device according to claim 1 wherein said second annealing includes two sub-steps, a first sub-step for reducing the resistance of the silicide layer and a second sub-step for forming a nitride layer in a surface layer of the silicide layer.

14. A method of producing a semiconductor integrated circuit device according to claim 1 wherein the silicide layer formed in the first annealing has at least a portion thereof exposed through a connecting hole, and wherein said second annealing is performed so as to turn the titanium silicide layer exposed through the connecting hole into a nitride layer.

15. A method of producing a semiconductor integrated circuit device according to claim 14 wherein said second annealing is performed a sufficient length of time to change the silicide into nitride through the entire depth of the silicide layer.