Quad processor
First Claim
Patent Images
1. A multiple-processing and contamination-free plasma etching system, comprising:
- plural, single-wafer plasma etching vessels each having an ingress and egress defining port that are arrayed about a predetermined spacial locus in such a way that the several ports thereof are accessible form a single location spaced from the several ports;
a wafer queuing station spaced with the plural vessels along the same predetermined spacial locus defining a wafer access port accessible from said single location;
plural valve means individually coupled to corresponding ones of said plural, single-wafer plasma etching vessel ingress and egress ports and to said wafer queuing station wafer access port;
single-wafer transfer means disposed at said single location and cooperative with corresponding ones of said plural valve means for moving wafers from and to said wafer access port of said queuing station from and to selected ones of said single-wafer plasma etching vessels through the associated one of said ingress and egress ports thereof; and
processor means for controlling said vessels, said transfer means and said valve means to provide selectable single or multistep processing of wafers in said queuing station in one or more of said etching vessels.
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Abstract
The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. In this manner a wafer can be processed as soon as a vessel becomes available.
140 Citations
25 Claims
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1. A multiple-processing and contamination-free plasma etching system, comprising:
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plural, single-wafer plasma etching vessels each having an ingress and egress defining port that are arrayed about a predetermined spacial locus in such a way that the several ports thereof are accessible form a single location spaced from the several ports; a wafer queuing station spaced with the plural vessels along the same predetermined spacial locus defining a wafer access port accessible from said single location; plural valve means individually coupled to corresponding ones of said plural, single-wafer plasma etching vessel ingress and egress ports and to said wafer queuing station wafer access port; single-wafer transfer means disposed at said single location and cooperative with corresponding ones of said plural valve means for moving wafers from and to said wafer access port of said queuing station from and to selected ones of said single-wafer plasma etching vessels through the associated one of said ingress and egress ports thereof; and processor means for controlling said vessels, said transfer means and said valve means to provide selectable single or multistep processing of wafers in said queuing station in one or more of said etching vessels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A system for providing semiconductor wafer etch processing of a plurality of semiconductor wafers contained in a cassette in conjunction with a plurality of wafer etch chambers comprising:
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an array of wafer stations comprising; at least one wafer cassette queuing station adapted for containing a plurality of wafers in individual slots of a wafer containment cassette; a plurality of wafer etch vessels; means for providing gated entrance to said wafer etch vessels to provide in a first state sealed containment of an environment within each of said vessels and in a second state access to the vessel interior; means for transporting wafers between selected slots in a cassette at said queuing station and the interior of selected plasma etched vessels via said gated entrance means in said second state; processor means for sequencing wafers between associated slot positions in a cassette of said queuing stations and one or more of said plasma etch vessels in accordance with plasma processing commands associated with each wafer.
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Specification