Versatile interconnection bus

• US 4,734,909 A
• Filed: 08/21/1986
• Issued: 03/29/1988
• Est. Priority Date: 03/08/1982
• Status: Expired due to Fees

• Current Assignee: Sperry Corporation
• Original Assignee: Sperry Corporation
• Inventors: Petschauer, Thomas W., Thorsrud, Lee T., Bennett, Donald B.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/898,810
• Time in Patent Office: 586 Days
• Field of Search: 370/85, 370/89, 370/94, 370/88, 340/825.5, 340/825.51
• US Class Current: 370/462
• CPC Class Codes: F02B 2075/025 two
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator
• CPC Class Codes: G06F 13/4217 with synchronous protocol

Abstract

A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Claims

1. In a bus arbitration system comprising a bus which consists of a plurality of bus lines and a plurality of bus contention means coupled to said bus lines that are each capable of contending for control of said bus, the improvement comprising clock means for producing clock signals of at least first and second signal phases, wherein each of said bus contention means comprise

drive means coupled to each of said plurality of lines of said bus and constructed to unconditionally drive each line of said bus to a first logic state during said first clock signal phase in order to precharge the capacitance associated with said bus lines and to conditionally drive each of said bus lines to either a first logic state, or to a second logic state,, in accordance with an established priority code during said second clock signal phase,

read means for reading the logic state of said bus lines during said second clock signal phase,

priority determining means for comparing the logic state patterns of the bus lines which are associated with the priority codes of each of said bus contention means with the logic state pattern that is established by said conditionally driven lines and for removing all of said bus contention means from contention for said bus for which said logic state patterns do not match.

2. In a bus arbitration system as claimed in claim 1 the further improvement wherein said priority determining means comprises priority resolution means which resolves said bus contention among those bus contention means which were conditionally driven to said first logic state during said second clock signal phase based upon a predetermined priority scheme.

3. In a bus arbitration system as in claim 1 the further improvement wherein said system comprises default means which establishes a predetermined bus contention default priority order when none of said logic state patterns of said bus lines of said bus contention means match said logic state pattern of said conditionally driven lines.

4. In a bus arbitration system as in claim 1 the further improvement comprising selectively alterable reconfiguration means for selectively specifying the number of bus lines that are coupled to said bus contention means, and hence for selectively specifying the number of bus contention means that may be included in at least one group of bus contention means which is capable of contending for the control of said bus.

5. In a bus arbitration system as claimed in claim 4 the further improvement wherein said reconfigurable means is capable of specifying the number of bus lines that may be utilized by each bus contention means of a specified group of bus contention means.

6. In a bus arbitration system as claimed in claim 5 the further improvement comprising a plurality of interconnection pins wherein said reconfigurable means is capable of specifying the ones of said pins which are to be utilized by each of said specified group of bus contention means.

7. In a bus arbitration system as in claim 2 the further improvement comprising selectively alterable reconfiguration means for selectively specifying the number of bus lines that are coupled to said bus contention means, and hence for selectively specifying the number of bus contention means that may be included in at least one group of bus contention means which is capable of contending for the control of said bus.

8. In a bus arbitration system as claimed in claim 7 the further improvement wherein said reconfigurable means is capable of specifying the number of bus lines that may be utilized by each bus contention means of a specified group of bus contention means.

9. In a bus arbitration system as claimed in claim 8 the further improvement comprising a plurality of interconnection pins wherein said reconfigurable means is capable of specifying the ones of said pins which are to be utilized by each of said specified group of bus contention means.

10. In a bus arbitration system as in claim 9 the further improvement wherein said system comprises default means which establishes a predetermined bus contention default priority order when none of said logic state patterns of said bus lines of said bus contention means match said logic state pattern of said conditionally driven lines.

11. A bus interface having a fixed number of connecting pins comprising timing means that provides successive timing clock phases, first means comprising means for supplying first binary signals which are selectively representative of one or more of the following Group A types of coded information:

(1) data, (2) address, or (3) function, a plurality of Group A interconnection pins, and means for selecting the number of said Group A pins which may receive said first binary signals representative of each type of Group A information during any given clock phase wherein the number of pins may vary from zero for each type of Group A information, to all of said Group A pins, and second means comprising means for supplying second binary signals which are selectively representative of one or more of the following Group B types of coded information;

(1) arbitration priority, (2) slave identification, (3) address, or (4) function, a plurality of Group B interconnection pins, and means for selecting the number of Group B pins which may receive said second binary signals representative of each type of Group B information during any given clock phase, wherein the number of pins may vary from zero to all of said Group B pins for each type of Group B information, and timing means for controlling the timing of said first and said second binary signals so that said first binary signals that are coupled to their selected Group B pins during a clock phase that succeeds the clock phase during which said second binary signals are coupled to their selected Group A pins.

12. A bus interface as claimed in claim 11 further comprising transaction configuration means for selectively controlling whether said signals representative of each type of coded information supplied by said first and said second means are coupled on said bus in a multiplexed manner or whether separate ones of said pins are reserved for one particular type of information.