Interference cancellation system

• US 4,736,455 A
• Filed: 10/21/1986
• Issued: 04/05/1988
• Est. Priority Date: 12/23/1985
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Murase, Takehiro, Matsue, Hideaki
• Primary Examiner(s): Masinick, Michael A.
• Application Number:
  US06/921,093
• Time in Patent Office: 532 Days
• Field of Search: 455/138, 455/139, 455/272, 455/273, 455/276, 455/278
• US Class Current: 455/138
• CPC Class Codes: H04B 1/126 having multiple inputs, e.g. auxiliary antenna for receiving interfering signal aerials in general H01Q
• CPC Class Codes: H04B 7/0854 using error minimizing algorithms, e.g. minimum mean squared error [MMSE], "cross-correlation" or matrix inversion

Abstract

An interference cancellation system at a receiver side for digital radio system has a first quadrature phase detector for demodulating the main signal. A second quadrature phase detector (or a phase detector) is supplied with the same reference carrier and clock signal as that of the first quadrature phase detector, for phase detecting an interference signal. A decision circuit is coupled with the first quadrature phase detector to provide a baseband signal. An error signal detector provides a difference between a decision level of a digital signal and an input of the decision circuit due to the interference signal. A correlation device provides a correlation signal between an error signal and a phase detected interference signal. A control device provides a compensation signal which has the same amplitude and anti-phase as those of the interference component included in the main signal according to the correlation signal. A combiner combines the main signal with the compensation signal to provide a compensated main signal which is free from interference. A combiner and a control means may be inserted either in an RF stage or an IF stage, or in a baseband stage. An error signal detector and decision circuit are implemented by an A/D converter. A correlation means is implemented by a digital or analog multiplier and integrators.

Claims

1. An interference cancellation system comprising:

(a) a main signal reception means for receiving a main signal of a desired digital signal and an undesired interference signal;

(b) an auxiliary signal reception means for receiving said undesired interference signal;

(c) a control means for providing a compensation signal having an amplitude and anti-phase equal to an amplitude and anti-phase of the undesired interference signal in the main signal;

(d) a combiner for combining the main signal and an output of said control means to cancel the undesired interference signal in the main signal;

(e) a quadrature phase detector for demodulating the main signal;

(f) a phase detector for phase detecting the undesired interference signal, said phase detector being supplied with a clock signal obtained by said quadrature phase detector for the main signal;

(g) a decision circuit coupled with an output of said quadrature phase detector, to provide a demodulated digital signal;

(h) an error signal detector for providing a difference between a decision level of said desired digital signal detector and an output of said quadrature phase detector;

(i) a correlation means for providing a correlation between an output of said error signal detector and an output of the phase detector for said undesired interference signal; and

(j) said control means being controlled by an output of said correlation means.

2. An interference cancellation system according to claim 1, wherein said combiner is inserted in one of an IF stage and a RF stage.

3. An interference cancellation system according to claim 1, wherein said combiner is inserted in a baseband stage.

4. An interference cancellation system according to claim 1, wherein said control means comprises a variable attenuator and a variable phase shifter.

5. An interference cancellation system according to claim 1, wherein said control means is implemented by a quadrature amplitude modulator which comprises a pair of bipolar variable attenuators, a 90°

phase shifter coupled with an input of one of said variable attenuators, and a combiner for combining outputs of said variable attenuators.

6. An interference cancellation system according to claim 1, wherein said phase detector for phase detecting said undesired interference signal is a quadrature phase detector.

7. An interference cancellation system according to claim 1, wherein said correlation means comprises at least two multipliers for providing a product of an error signal of an in-phase component and said undesired interference signal, and a product of an error signal of a quadrature component and said undesired interference signal, and at least two low-pass filters each coupled with a related output of said multipliers, so that outputs of said low-pass filters control amplitude and phase of said control means.

8. An interference cancellation system according to claim 7, wherein said multiplier is implemented by an exclusive-OR circuit, and said low-pass filter is implemented by a digital integrator.

9. An interference cancellation system according to claim 1, wherein said correlation means has a switch which supplies a correlation signal to said control means only when a reception signal is in a synchronized condition, and said switch supplies a fixed control signal to said control means when said reception signal is in an asynchronous condition.

10. An interference cancellation system according to claim 1, wherein said error signal detector is implemented by an A/D converter, which doubles as a decision circuit.