Microwave multiport multilayered integrated circuit chip carrier

• US 4,739,448 A
• Filed: 06/25/1984
• Issued: 04/19/1988
• Est. Priority Date: 06/25/1984
• Status: Expired due to Term

• Current Assignee: Mesc Electronic Systems, Inc.
• Original Assignee: Magnavox Government and Industrial Electronics Company
• Inventors: Rowe, David A., Dietterle, Robert E., Lao, Binneg Y.
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): THOMPSON, GREGORY D
• Application Number:
  US06/623,990
• Time in Patent Office: 1,394 Days
• Field of Search: 361/403, 361/410, 361/412, 361/413, 361/414, 361/386, 361/388
• US Class Current: 361/719
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/10161 with a rectangular active surface
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01P 3/088 : Stacked transmission lines
• CPC Class Codes: H05K 1/0237 : High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 3/3431 : Leadless components

Abstract

A multilayered integrated circuit chip carrier has a top layer, a signal line layer, a ground layer, a power conductor layer, and a bottom layer with a separating layer between adjacent layers. Each layer has coplanar conductive and dielectric portions, the separating layers being primarily dielectric. The top layer supports an integrated circuit chip and signal launcher pads on the bottom layer couple signal and power lines of a printed circuit board to spaced points about the bottom layer periphery and substantially constant signal line impedance is achieved. The signal line layer is separated from the power conductor layer by a ground plane layer. Conductive via through pads are placed in the separating layers to form a plurality of separate conductive paths from each of the bottom and top layers to each of the signal line and power conductor layers. Via through pads are also placed in the separating layers to break up cavities and thus increase cavity resonance above signal frequencies and are placed in the signal line layer to provide signal line isolation. Thermal columns of via pads in the separating layers and conductive portions in the other layers under the chip provide chip cooling. Large grounded conductive areas in the top and bottom layers reduce unwanted signal coupling to the external environment. A capacitive coupling on the top layer between a power conductor and ground provides power line isolation.

Claims

1. Carrier apparatus for an integrated circuit chip having power and signal terminals, the carrier apparatus adapted to be mounted on a printed circuit board comprising:

a printed circuit board having conductive signal lines and power lines;

a plurality of superimposed layers including a top layer and a bottom layer;

a signal line layer and a power conductor layer being between said top and bottom layers and separated from each other and said top and bottom layers by a respective separating layer;

at least one separating layer positioned on either side of said signal line layer and on either side of said power conductor layer;

said top layer having a mounting location for the chip;

first and second conductive portions in said top layer adjacent the periphery of said mounting location;

conductive via pads in each of said separating layers conductively coupling predetermined conductive portions of one adjacent layer to predetermined conductive portions of another adjacent layer, each of said pads being surrounded by dielectric portions of its respective separating layer;

first conductive portions in said bottom layer coupling to the printed circuit board signal lines;

second conductive portions in said bottom layer coupling to the printed circuit board power lines;

said signal line layer having coplanar conductive signal lines each having first and second ends;

said signal lines being separated by coplanar dielectric portions;

said via pads comprising first via pads in respective separating layers coupling said bottom layer first conductive portions to respective first ends of respective signal lines in said signal line layer;

said via pads comprising second via pads in the separating layer between said top layer and said signal line layer coupling said second ends of said signal lines to respective said first conductive portions in said top layer adjacent said mounting location;

said power conductor layer having coplanar conductive power conductors separated by coplanar dielectric portions;

said via pads comprising third via pads in the separating layer between said power conductor layer and said bottom layer coupling said bottom layer second conductive portions to respective conductors of said power conductors of said power conductor layer;

said via pads comprising fourth via pads in respective separating layers coupling said power conductors to respective said second conductive portions of said top layer adjacent said mounting location;

said separating layer having dielectric portions electrically insulating said signal lines and power conductors from each other and electrically insulating said signal lines and power conductors from said top and bottom layers.

2. The apparatus of claim 1 wherein said top layer is comprised of a grounded conductive portion coplanar with and substantially larger in area than said top layer first and second conductive portions;

said top layer having coplanar dielectric portions electrically insulating said first and second conductive portions and said grounded conductive portion from each other;

said bottom layer is comprised of a grounded conductive portion coplanar with and substantially larger in area than said bottom layer first and second conductive portions;

said bottom layer having coplanar dielectric portions electrically insulating said first and second conductive portions and said bottom layer grounded conductive portion from each other.

3. The apparatus of claim 2 including a conductive cover having a top and sides depending therefrom;

said sides having bottom edges;

means bonding the bottom edges of said sides to said grounded conductive portion of the top surface of said top layer;

said edges enclosing an area of said top surface including said mounting location and the area above said second and fourth via pads.

4. The apparatus of claim 2 including a bypass capacitor mounted to said top layer and conductively coupled between said fourth via pads and said grounded conductive portion of said top layer.

5. The apparatus of claim 1 wherein said via pads comprise sixth via pads coupling said top layer at said mounting location to a conductive portion of said bottom layer through conductive portions in said signal line layer and said power conductor layer and intermediate separating layers;

said sixth via pads being beneath said mounting location, each of said conductive portions being surrounded by dielectric portions in its respective layer.

6. The apparatus of claim 5 including an integrated circuit chip having signal terminals and power terminals;

said chip being mounted on said top layer mounting location;

a first conductor connecting each said top layer first conductive portion to a respective chip signal terminal;

a second conductor connecting each said top layer second conductive portion to a respective chip power terminal.

7. The apparatus of claim 1 wherein said signal line layer has grounded conductive portions;

said power conductor layer has grounded conductive portions;

said via pads comprise seventh via pads in said separating layers between said signal line layer grounded conductive portions and said power conductor layer grounded conductive portions;

said seventh via pads being spaced from one another in the plane of their respective separating layers to break up cavities so that cavity resonant frequencies are substantially increased beyond signal frequencies and provide isolation between said signal lines.

8. The apparatus of claim 1 wherein said bottom layer first conductive portions comprise a conductive signal launcher pad overlying and in conductive contact with the printed circuit board signal lines providing substantially constant impedance from the printed circuit board signal lines to said top layer.

9. The apparatus of claim 8 including at least a pair of ground lines on the printed circuit board and coplanar with each said printed circuit board signal line;

a ground line of said pair of ground lines being on either side of and insulated from each printed circuit board signal line;

a spacing B being between said pair of printed circuit board ground lines;

each printed circuit board signal line having a width W;

the relative dimensions of B and W being determined to provide a predetermined printed circuit board signal line impedance;

said bottom layer comprising a grounded conductive area having a plurality of substantially straight sides;

at least one of said bottom layer conductive area sides having at least one recessed notched opening having spaced side edges and an end edge;

said opening side edges being spaced apart by a dimension D that is greater than dimension B;

said signal launcher pad being elongated and having a lateral dimension C that is less than W;

said elongated launcher pad extending into said notched opening and spaced from said opening side edges and end edge and said launcher pad having one end adjacent to said end edge of said opening and said launcher pad one end having a truncated triangular shape;

the distance between said truncated triangular end and said end edge of said notched opening being greater than E/2 where E is the smaller of the quantity (W-C) and the quantity (D-B).

10. The apparatus of claim 9 including a said notched opening and a said signal launcher pad in said bottom layer for each printed circuit board signal line.

11. The apparatus of claim 1 wherein said via pads in each said separating layer are progressively larger in size than the size of said via pads in the next said separating layer nearer said top layer.

12. The apparatus of claim 2 wherein said plurality of layers includes an internal ground plane layer positioned between said signal line layer and said power conductor layer;

said ground plane layer having a grounded conductive portion;

said plurality of layers comprising a separating layer between said ground plane layer and said signal line layer and having dielectric portions electrically insulating said ground plane layer grounded conductive portion from said signal lines;

said plurality of layers comprising a separating layer between said ground plane layer and said power conductor layer and having dielectric portions electrically insulating said ground plane layer grounded conductive portion from said power conductors;

said via pads comprising fifth via pads in respective separating layers conductively coupling said grounded conductive portion of said ground plane layer to said grounded conductive portion in at least one of said top layer and said bottom layer through respective conductive portions in layers intermediate said ground plane layer and said at least one of said top layer and said bottom layer.

13. The apparatus of claim 12 wherein said fifth via pads couple said grounded conductive portion of said ground plane layer to said grounded conductive portions of both said top and bottom layers.

14. The apparatus of claim 13 wherein said via pads comprise sixth via pads in respective separating layers for coupling a conductive portion of said top layer at said mounting location to conductive portions in said signal line layer, ground plane layer, power conductor layer and bottom layer for thermal conductivity between said top layer mounting location conductive portion and said bottom layer grounded conductive portion.

15. The apparatus of claim 12 wherein said signal line layer has grounded conductive portions;

said power conductor layer has grounded conductive portions;

said fifth via pads including via pads in said separating layer between said signal line layer and said ground plane layer connecting said signal line layer grounded conductive portions and said ground plane layer grounded conductive portion;

said fifth via pads including via pads in said separating layer between said power conductor layer and said ground plane layer connecting said power conductor layer grounded conductive portions and said ground plane layer grounded conductive portion and said fifth via pads being spaced from one another in the plane of their respective separating layers to break up cavities so that cavity resonant frequencies are substantially increased beyond signal frequencies and provide isolation between said signal lines.

16. The apparatus of claim 1 including a mounting location conductive portion in said top layer substantially coextensive with said mounting location;

said conductive via pads including electrically and thermally conductive thermal via pads in each of said separating layers, and thermally conductive portions in each of said signal line layer, power conductor layer and bottom layer being vertically beneath said mounting location conductive portion;

said mounting location conductive portion, thermal via pads and thermally conductive portions being conductively bonded to one another to form a thermally conductive path between said mounting location conductive portion and said bottom layer thermally conductive portion whereby an integrated circuit chip mounted on said top layer at said mounting location will have heat transfer to said bottom layer.

17. The apparatus of claim 12 including a mounting location conductive portion in said top layer substantially coextensive with said mounting location;

said conductive via pads including electrically and thermally conductive thermal via pads in each of said separating layers, and thermally conductive portions in each of said signal line layer, ground plane layer, power conductor layer and bottom layer being vertically beneath said mounting location conductive portion;

said mounting location conductive portion, thermal via pads and thermally conductive portions being conductively bonded to one another to form a thermally conductive path between said mounting location conductive portion and said bottom layer thermally conductive portion whereby an integrated circuit chip mounted on said top layer at said mounting location will have heat transfer to said bottom layer.

18. The apparatus of claim 16 or 17 including an integrated circuit chip having signal and power terminals and being conductively bonded to said mounting location conductive portion;

coupling means to conductively couple said chip signal and power terminals to said first and second conductive portions, respectively in said top layer.

19. The apparatus of claim 18 wherein said mounting location conductive portion is recessed into said separating layer immediately below said top layer so that the top surface of said chip is approximately coplanar with the top surface of said top layer whereby the length of said coupling means is shortened.

20. The apparatus of claim 18 wherein said apparatus has an opening therein;

said chip being placed in said opening whereby the top surface of said chip is approximately coplanar with the top surface of said top layer.

21. Apparatus for use with a printed circuit board comprising:

a layer of dielectric material;

a printed circuit board having at least one conductive signal line;

at least a pair of ground lines on the printed circuit board coplanar with said printed circuit board signal line;

a ground line of said pair of ground lines being on either side of and insulated from said printed circuit board signal line and having a spacing B between said pair of printed circuit board ground lines;

the printed circuit board signal line having a width W;

the relative dimensions of B and W being determined to provide a predetermined printed circuit board signal line impedance;

a grounded conductive area being deposited on said dielectric layer;

said grounded conductive area having a plurality of substantially straight sides;

at least one of said grounded conductive area sides having at least one recessed notched opening having spaced side edges and an end edge;

said opening side edges being spaced apart by a dimension D that is greater than dimension B;

a conductive signal launcher pad overlying and in conductive contact with said printed circuit board signal line;

said signal launcher pad being elongated and having a lateral dimension C that is less than W;

said launcher pad extending into said notched opening and spaced from said opening side edges and said end edge;

said launcher pad having one end adjacent to said end edge of said opening;

said launcher pad one end having a truncated triangular shape;

the distance between said truncated triangular end and said end edge of said notched opening being greater than E/2 where E is the smaller of the quantity (W-C) and the quantity (D-B) whereby a substantially constant impedance is provided from said printed circuit board signal line to said conductive area.

22. The apparatus of claim 21 including a plurality of said signal lines on said printed circuit board;

a said notched opening in said conductive area and a signal launcher pad for each said printed circuit board signal line.