Microwave multiport multilayered integrated circuit chip carrier
First Claim
1. Carrier apparatus for an integrated circuit chip having power and signal terminals, the carrier apparatus adapted to be mounted on a printed circuit board comprising:
- a printed circuit board having conductive signal lines and power lines;
a plurality of superimposed layers including a top layer and a bottom layer;
a signal line layer and a power conductor layer being between said top and bottom layers and separated from each other and said top and bottom layers by a respective separating layer;
at least one separating layer positioned on either side of said signal line layer and on either side of said power conductor layer;
said top layer having a mounting location for the chip;
first and second conductive portions in said top layer adjacent the periphery of said mounting location;
conductive via pads in each of said separating layers conductively coupling predetermined conductive portions of one adjacent layer to predetermined conductive portions of another adjacent layer, each of said pads being surrounded by dielectric portions of its respective separating layer;
first conductive portions in said bottom layer coupling to the printed circuit board signal lines;
second conductive portions in said bottom layer coupling to the printed circuit board power lines;
said signal line layer having coplanar conductive signal lines each having first and second ends;
said signal lines being separated by coplanar dielectric portions;
said via pads comprising first via pads in respective separating layers coupling said bottom layer first conductive portions to respective first ends of respective signal lines in said signal line layer;
said via pads comprising second via pads in the separating layer between said top layer and said signal line layer coupling said second ends of said signal lines to respective said first conductive portions in said top layer adjacent said mounting location;
said power conductor layer having coplanar conductive power conductors separated by coplanar dielectric portions;
said via pads comprising third via pads in the separating layer between said power conductor layer and said bottom layer coupling said bottom layer second conductive portions to respective conductors of said power conductors of said power conductor layer;
said via pads comprising fourth via pads in respective separating layers coupling said power conductors to respective said second conductive portions of said top layer adjacent said mounting location;
said separating layer having dielectric portions electrically insulating said signal lines and power conductors from each other and electrically insulating said signal lines and power conductors from said top and bottom layers.
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Accused Products
Abstract
A multilayered integrated circuit chip carrier has a top layer, a signal line layer, a ground layer, a power conductor layer, and a bottom layer with a separating layer between adjacent layers. Each layer has coplanar conductive and dielectric portions, the separating layers being primarily dielectric. The top layer supports an integrated circuit chip and signal launcher pads on the bottom layer couple signal and power lines of a printed circuit board to spaced points about the bottom layer periphery and substantially constant signal line impedance is achieved. The signal line layer is separated from the power conductor layer by a ground plane layer. Conductive via through pads are placed in the separating layers to form a plurality of separate conductive paths from each of the bottom and top layers to each of the signal line and power conductor layers. Via through pads are also placed in the separating layers to break up cavities and thus increase cavity resonance above signal frequencies and are placed in the signal line layer to provide signal line isolation. Thermal columns of via pads in the separating layers and conductive portions in the other layers under the chip provide chip cooling. Large grounded conductive areas in the top and bottom layers reduce unwanted signal coupling to the external environment. A capacitive coupling on the top layer between a power conductor and ground provides power line isolation.
207 Citations
22 Claims
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1. Carrier apparatus for an integrated circuit chip having power and signal terminals, the carrier apparatus adapted to be mounted on a printed circuit board comprising:
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a printed circuit board having conductive signal lines and power lines; a plurality of superimposed layers including a top layer and a bottom layer;
a signal line layer and a power conductor layer being between said top and bottom layers and separated from each other and said top and bottom layers by a respective separating layer;
at least one separating layer positioned on either side of said signal line layer and on either side of said power conductor layer;said top layer having a mounting location for the chip;
first and second conductive portions in said top layer adjacent the periphery of said mounting location;conductive via pads in each of said separating layers conductively coupling predetermined conductive portions of one adjacent layer to predetermined conductive portions of another adjacent layer, each of said pads being surrounded by dielectric portions of its respective separating layer; first conductive portions in said bottom layer coupling to the printed circuit board signal lines; second conductive portions in said bottom layer coupling to the printed circuit board power lines; said signal line layer having coplanar conductive signal lines each having first and second ends;
said signal lines being separated by coplanar dielectric portions;said via pads comprising first via pads in respective separating layers coupling said bottom layer first conductive portions to respective first ends of respective signal lines in said signal line layer; said via pads comprising second via pads in the separating layer between said top layer and said signal line layer coupling said second ends of said signal lines to respective said first conductive portions in said top layer adjacent said mounting location; said power conductor layer having coplanar conductive power conductors separated by coplanar dielectric portions; said via pads comprising third via pads in the separating layer between said power conductor layer and said bottom layer coupling said bottom layer second conductive portions to respective conductors of said power conductors of said power conductor layer; said via pads comprising fourth via pads in respective separating layers coupling said power conductors to respective said second conductive portions of said top layer adjacent said mounting location; said separating layer having dielectric portions electrically insulating said signal lines and power conductors from each other and electrically insulating said signal lines and power conductors from said top and bottom layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. Apparatus for use with a printed circuit board comprising:
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a layer of dielectric material; a printed circuit board having at least one conductive signal line;
at least a pair of ground lines on the printed circuit board coplanar with said printed circuit board signal line;
a ground line of said pair of ground lines being on either side of and insulated from said printed circuit board signal line and having a spacing B between said pair of printed circuit board ground lines;
the printed circuit board signal line having a width W;
the relative dimensions of B and W being determined to provide a predetermined printed circuit board signal line impedance;a grounded conductive area being deposited on said dielectric layer;
said grounded conductive area having a plurality of substantially straight sides;
at least one of said grounded conductive area sides having at least one recessed notched opening having spaced side edges and an end edge;
said opening side edges being spaced apart by a dimension D that is greater than dimension B;a conductive signal launcher pad overlying and in conductive contact with said printed circuit board signal line;
said signal launcher pad being elongated and having a lateral dimension C that is less than W;
said launcher pad extending into said notched opening and spaced from said opening side edges and said end edge;
said launcher pad having one end adjacent to said end edge of said opening;
said launcher pad one end having a truncated triangular shape;
the distance between said truncated triangular end and said end edge of said notched opening being greater than E/2 where E is the smaller of the quantity (W-C) and the quantity (D-B) whereby a substantially constant impedance is provided from said printed circuit board signal line to said conductive area. - View Dependent Claims (22)
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Specification