Method for buffered serial peripheral interface (SPI) in a serial data bus

• US 4,742,349 A
• Filed: 05/22/1986
• Issued: 05/03/1988
• Est. Priority Date: 05/22/1986
• Status: Expired due to Term

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: Chrysler Corporation (Stellantis NV)
• Inventors: McCambridge, John M., Miesterfeld, Frederick O. R., Fassnacht, Ronald E., Nasiadka, Jerry M.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US06/866,628
• Time in Patent Office: 712 Days
• Field of Search: 340/825.5, 340/825.51, 370/85
• US Class Current: 370/447
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4213 with asynchronous protocol
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle

Abstract

In a communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having either a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, a method to transmit and receive data in a buffered serial peripheral interface (SPI) mode of operation in conjunction with a method of arbitrating data on the data bus.

Claims

1. In a communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having either a serial communication interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and a input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit with a control line, an idle line and a buffer, a method of transmitting data in a buffered SPI mode of operation comprising:

a bit-wise contention and a deterministic priority access method to (a) resolve contentions among user microprocessors that try to send messages at the same time and to (b) synchronize each data byte and to (c) allow the priority of an ID byte of the message to determine which of a plurality of messages will be sent first in the case of a contention, the determination of which user microprocessor transmits first being made without losing bus time when contention occurs; and

checking to see whether another user microprocessor with higher priority is already transmitting on the data bus by reading the state of the control line, waiting if such is the case;

if no other user microprocessor is already transmitting on the data bus, loading data into the buffer on the bus interface IC;

signaling the data bus that transmission is about to occur by latching the state of the control line to a predetermined state;

checking to see whether a start bit is already on the data bus, waiting at least 2 idle bit times if no start bit is on the data bus before generating a start bit;

sending a signal to the data bus by setting the idle time for predetermined state indicating that the bus is busy;

waiting for the end of the start bit to occur;

sending out two bytes of data to the bus from the buffer separated by bus interface IC-generated start and stop bits if not blocked by the bitwise contention and deterministic priority access method in the bus interface IC;

locking out the user microprocessor from the buffer on the bus interface integrated circuit;

waiting for the second stop bit to occur;

arranging data in the buffer to get the first byte in, such that the most significant byte out to the user microprocessor will be sent first;

locking out data on the bus via the bus interface integrated circuit from the buffer;

waiting for the reading of the data;

repeating the previous steps if more data is to be transmitted;

waiting 11 bit times if the data transmission is complete; and

releasing the bus to an idle condition.

2. In a communication system for the transmission of messages through a data bus between one or more user microprocessor coupled to the data bus, the user microprocessors having either a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, with a control line, an idle line and a buffer a method of receiving data in a buffered SPI mode of operation comprising:

a bit-wise contention and a deterministic priority access method to (a) resolve contentions among user microprocessors that try to send messages at the same time and to (b) synchronize each data byte and to (c) allow the priority of an ID byte of the message to determine which of a plurality of messages will be sent first in the case of a contention, the determination of which user microprocessor transmits first being made without losing bus time when contention occurs; and

waiting for a start bit to appear on the data bus;

signaling other user microprocessors that the data bus is busy;

waiting for the end of the start bit to occur;

waiting for the data to be read, locking the buffer from the bus if the data has not been read and waiting for the bus to return to an idle state before rechecking to see whether a start bit has appeared on the data bus;

if all of the data has been read into the buffer, clock the buffer;

allow data and stop bit to enter the data bus;

allowing the user microprocessor to clock the buffer;

waiting for the end of the stop bit;

waiting for the occurrence of the start bit on the data bus before reading the rest of the data from the bus, but releasing the data bus to an idle condition if ten idle bit times follow the first entry of data;

waiting for the stop bit time to occur and waiting for the end of the stop bit;

checking to see whether a start bit has appeared on the bus and repeating the above procedures if more transmission is to occur;

waiting for ten idle bit times if a start bit is not on the bus and signaling the rest of the user microprocessors that the bus is in an idle condition.