Digital processor for radar signals which can perform adaptive suppression of clutter means of a parametric estimator

• US 4,742,353 A
• Filed: 04/16/1987
• Issued: 05/03/1988
• Est. Priority Date: 07/27/1984
• Status: Expired due to Fees

• Current Assignee: Selenia-Industrie Elettroniche Associate SPA
• Original Assignee: Selenia-Industrie Elettroniche Associate SPA
• Inventors: D'Addio, Egidio, Farina, Alfonso
• Primary Examiner(s): Blum, Theodore M.
• Assistant Examiner(s): GREGORY, BERNARR E
• Application Number:
  US07/039,751
• Time in Patent Office: 383 Days
• Field of Search: 342/93, 342/159-162, 342/195, 364/724
• US Class Current: 342/159
• CPC Class Codes: G01S 13/5244 Adaptive clutter cancellation specially adapted for airborne MTI, G01S13/5242
• CPC Class Codes: G01S 7/2923 based on data belonging to a number of consecutive radar periods

Abstract

A digital processor for radar signals which can perform adaptive suppression of the disturbance clutter and enhancement of the useful signal of given Doppler frequency. It can approximate the principle of operation of the optimum processor, which is that processor which maximizes the signal-to-noise ratio. Such processor can also cancel, in a adaptive manner, a clutter component having an approximately Gaussian power spectrum.

Claims

1. A radar signal digital processor which suppresses clutter disturbances and enhances useful signals of given Doppler frequency, comprising:

a finite impulse response filter (10);

an estimator of disturbance parameters (4);

a memory (5) coupled to an output of the estimator (4);

a weight synthesizer (8) coupled to a second output of the estimator (4) for calculating complex weights; and

a register (9) for storing the complex weights for output to the finite impulse response filter (10).

2. The radar signal digital processor of claim 1 wherein the estimator (4) comprises:

at least one complex multiplier (12);

at least one complex adder (14);

at least one modulus extractor (15);

a coherent limiter (19);

a divider (18);

at least two dividers by N (15);

at least two multipliers (20)

at least two adders (16)

at least one square root extractor (17);

means for selecting one of the areas of memory (5) which contains the inverse of the disturbance covariance matrix having zero Doppler; and

means for providing disturbance Doppler phase to weight synthesizer (8) for the calculation of the complex weights.

3. The radar signal digital processor of claim 2 in which weight synthesizer (8) comprises:

two registers (6) and (7);

at least two complex multipliers (21) and (22);

three shift registers (9), (24), (25); and

a phase generator (26) comprising a shift register (30), two registers (31) and (32), at least two complex conjugate extractors, a delay line (29) and a complex multiplier (28).