Power saving intermittently operated phase locked loop

• US 4,743,864 A
• Filed: 10/23/1986
• Issued: 05/10/1988
• Est. Priority Date: 10/23/1985
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd., Hitachi Video Engineering Incorporated
• Original Assignee: Hitachi, Ltd., Hitachi Video Engineering Incorporated
• Inventors: Watanabe, Hideaki, Kimura, Hidefumi, Ienaka, Masanori, Nakagawa, Jun'ichi, Kuwamoto, Yoshitomo
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/922,300
• Time in Patent Office: 565 Days
• Field of Search: 331/1 A, 331/14, 331/17, 331/25, 331/27, 455/343
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

In an intermittently operative phase-locked loop, in order to prevent the oscillator frequency from significantly changing at the time of turning on of an electric power source, a point in time at which a phase difference between clock signals respectively fed to a reference frequency divider and to a frequency divider for dividing the output frequency of a voltage-controlled oscillator becomes substantially zero is detected, and the two frequency dividers are initialized when the above-mentioned point in time is detected after turning on of the electric power source.

Claims

1. A phase-locked oscillator comprising:

a phase-locked loop which includes a reference oscillator, a reference frequency divider for dividing the output of said reference oscillator, a voltage-controlled oscillator, a first frequency divider for dividing the output of said voltage-controlled oscillator, a phase comparator for comparing respective phases of the output of said reference frequency divider and the output of said first frequency divider, and a loop filter generating a control voltage from the output of said phase comparator, said control voltage being applied to said voltage-controlled oscillator;

a first switch for interrupting intermittently an electric power supplied from an electric power source to at least one of said reference oscillator, said reference frequency divider, said first frequency divider, said phase comparator and said loop filter;

a second switch for interrupting intermittently said control voltage in synchronism with said first switch;

a control voltage hold circuit located between said second switch and said voltage-controlled oscillator for holding said control voltage at a time when said second switch is changed from ON-state to OFF-state;

a detecting circuit for detecting a transient at which said first switch is changed from an OFF-state to an ON-state; and

an initial state setting circuit responsive to a detecting operation of said detecting circuit for initializing said reference frequency divider and said first frequency divider.

2. A phase-locked oscillator according to claim 1, in which said detecting circuit is arranged to detect said transient in response to a signal for driving at least one of said first and second switches.

3. A phase-locked oscillator according to claim 1, in which said detecting circuit is arranged to detect said transient in response to an output signal of at least one of said first and second switches.

4. An intermittently operative phase-locked oscillator comprising:

a phase-locked loop which includes a voltage-controlled oscillator, a first frequency divider for dividing the output of said voltage-controlled oscillator, a reference oscillator, a second frequency divider for dividing the output of said reference oscillator, a phase comparator for comparing respective phases of the output of said first frequency divider and the output of said second frequency divider, and a loop filter generating a control voltage from the output of said phase comparator, said control voltage being applied to said voltage-controlled oscillator, a first switch for interrupting intermittently an electric power supplied to at least one of said first frequency divider, said reference oscillator, said second frequency divider, said phase comparator and said loop filter by an intermittent operation signal, and a control voltage hold circuit connected between said loop filter and said voltage-controlled oscillator for holding said control voltage during a period of interruption of the electric power supply;

a zero-phase detecting circuit for detecting a state in which a difference in instantaneous phase between a first clock signal fed into said first frequency divider and a second clock signal fed into said frequency divider becomes substantially zero so as to generate a zero-phase signal;

a preset pulse generating circuit for generating a preset pulse in synchronization with said zero-phase signal generated after said first switch is switched on; and

said first and second frequency dividers being arranged to be simultaneously initialized to each initial state by said preset pulse.

5. A phase-locked oscillator according to claim 4, in which said zero-phase detecting circuit includes a phase comparing circuit for generating a pulse having a pulse width corresponding to a phase difference between said first clock signal and said second clock signal, a pulse width discriminating circuit for discriminating said pulse width and a sampling-hold circuit for sampling the output forma said pulse width discriminating circuit to obtain said zero-phase signal.

6. A phase-locked oscillator according to claim 4, further comprising:

a second-switch for interrupting said output of said reference frequency divider and said output of said first frequency divider fed to said phase comparator;

a third switch connected between said control voltage-hold circuit and said loop filter; and

a control circuit for turning off said second switch and said third switch during a period from start of interruption of said electric power supply to a time when said zero-phase signal is first generated after applying said electric power supply.

7. A phase-locked oscillator according to claim 5 further comprising:

a second-switch for interrupting said output of said reference frequency divider and said output of said first frequency divider fed to said phase comparator;

a third switch connected between said control voltage-hold circuit and said loop filter; and

a control circuit for turning off said second switch and said third switch during a period from start of interruption of said electric power supply to a time when said zero-phase signal is first generated after applying said electric power.

8. A phase-locked oscillator according to claim 4 further comprising:

a second switch for interrupting said output of said reference frequency divider and said output of said first frequency divider fed to said phase comparator; and

a third switch connected between said control-voltage hold circuit and said loop filter; and

a control circuit for turning off said third switch during a period from start of interruption of said electric power to a time when said zero-phase signal is first generated after applying of said electric power and for turning off said second switch during a period from just after applying of said electric power to the time when said zero-phase signal is first generated after applying of said electric power.

9. A phase-lock oscillator according to claim 6 further comprising:

a driving circuit for generating a first intermittent signal and a second intermittent signal;

said first intermittent signal being caused to turn from its "ON" state into its "OFF" state after the time when said intermittent control signal turns from its "ON" state to its "OFF" state, and caused to turn from its "OFF" state to its "ON" state when said intermittent control signal turns from its "OFF" state to its "ON" state;

said second intermittent signal being caused to turn from its "ON" state to its "OFF" state after the time when said intermittent control signal turns from its "ON" state to its "OFF" state, and caused to turn from its "OFF" state to its "ON" state after the time when said intermittent control signal turns from its "OFF" state to its "ON" state;

a reset pulse generating circuit for generating a reset pulse in synchronism with turning of said second intermittent signal from its "OFF" state to its "ON" state;

said preset pulse generating circuit being reset into its initial state by said reset pulse; and

said first switch being caused to turn from its "ON" state to its "OFF" state in synchronism with turning of said first intermittent signal from its "ON" state to its "OFF" state.

10. A phase-locked oscillator according to claim 8, further comprising:

a driving circuit for generating a first intermittent signal and a second intermittent signal;

said first intermittent signal being caused to turn from its "ON" state to its "OFF" state after the time when said intermittent control signal turns from its "ON" state to its "OFF" state, and caused to immediately turn from its "OFF" state to its "ON" state when said intermittent control signal turns from its "OFF" state to its "ON" state;

said second intermittent signal being caused to turn from its "ON" state to its "OFF" state after the time when said intermittent control signal turns from its "ON" state to its "OFF" state, and caused to turn from its "OFF" state to its "ON" state after the time when said intermittent control signal turns from its "OFF" state to its "ON" state;

a reset pulse generating circuit for generating a reset pulse in synchronism with turning of said second intermittent signal from its "OFF" state it its "ON" state;

said preset pulse generating circuit being reset into its initial state by said reset pulse; and

said first switch being caused to turn from its "ON" state to its "OFF" state in synchronism with turning of said first intermittent signal from its "ON" state to its "OFF" state.

12. A phase-locked oscillator according to claim 10, in which said zero-phase detecting circuit is reset to its initial state by said reset pulse.

13. A phase-locked oscillator according to claim 4 further comprising:

a third frequency divider for dividing the output of said voltage-controller oscillator and for applying its output to said first frequency divider;

a fourth frequency divider for dividing the output of said reference oscillator and for applying its output to said second frequency divider.

14. A phase-locked oscillator according to claim 4 further comprising:

a multi-modulus prescaler interposed between said voltage-controlled oscillator and said first frequency divider having a plurality of frequency-division moduli one of which is selected by a selection signal, dividing the output signal from said voltage-controlled oscillator, and being power-supplied through said first switch;

said first frequency divider being constituted by a main frequency divider and a swallow frequency divider;

a frequency-division output signal being used as said first clock signal to be fed to respective clock terminals of said main frequency divider and said swallow frequency divider, a frequency-division output signal of said swallow frequency divider being fed back to said multi-modulus prescaler as said selection signal, a frequency-division output signal of said main frequency divider being fed to said phase comparator;

a modulating circuit for modulating a level of said selection signal with a suitable signal during a period from after switching on again of said electric power supply by said intermittent operation control signal till said zero-phase signal is generated at first after switching on of said electric power supply.

15. A phase-locked oscillator according to claim 14, in which said modulating circuit is continuously energized with a power supply while said multi-modulus prescaler is intermittently energized with said electric power supply through said first switch, said modulating circuit keeps said selection signal applied to said multi-modulus prescaler at a "high" level or a "low" level or a "high impedance" level while said first switch is in its off-state.

11. A phaes-locked oscillator according to calim 9, in which said zero-phase detecting circuit is reset to its initial state by said reset pulse.

16. An intermittently operative phase-locked oscillator comprising:

a phase-locked loop which includes a voltage-controlled oscillator, a first frequency divider for dividing the output of said voltage-controlled oscillator, a reference oscillator, a second frequency divider for dividing the output of said reference oscillator, a phase comparator for comparing respective phases of the output of said first frequency divider and the output of said second frequency divider, a loop filter generating a control voltage from the output of said phase comparator and applying said control voltage to said voltage-controlled oscillator, and a first switch for interrupting an electric power supply by an intermittent operation control signal for at least said first frequency divider and said second frequency divider, comprising;

a zero-phase detecting circuit for detecting that a difference in instantaneous phase between a first clock signal to said first frequency divider and a second clock signal to said seccond frequency divider becomes substantially zero so as to generate a zero-phase signal;

a preset pulse generating circuit for generating a preset pulse in synchronization with said zero-phase signal generated at first after said electric power supply for said first and second frequency dividers is switched on by said intermittent control signal; and

a control circuit for generating a first gate signal to turn off two second switches and to make a charge pump circuit in a "high impedance" state during a period from just before interruption of said electric power supply by said intermittent operation control signal till said zero-phase signal is generated at first after switching on of said electric power supply, said first and second frequency dividers being arranged to be simultaneously initialized to each initial state by said preset pulse, said phase comparator being constituted by said two second switches, a phase comparing circuit and said charge pump circuit, said two second switches interrupting each of said outputs of said first and second frequency dividers into said phase comparing circuit in response to said first gate signal, said charge pump circuit converting an output of said phase comparing circuit into analog voltage signal and becoming in a "high impedance" state in response to said first gate signal.

17. A phase-locked oscillator according to claim 16 in which at least said first frequency divider and said second frequency divider are constituted by CMOS circuits, and are provided with CMOS input gate circuits respectively inserted into input stages of said first and second frequency divider, and said CMOS circuit part and said CMOS input gate circuits are continuously energized with a power source voltage to keep the output of said CMOS input gate circuits at a "high" level or at a "low" level during a period corresponding to the "OFF" state of said intermittent operation control signal.

18. A phase-locked oscillator according to claim 17 further comprising:

a multi-modulus prescaler interposed between said voltage-controlled oscillator and said one of CMOS input gate circuit followed by said first frequency divider having a plurality of frequency-division moduli one of which is selected by a selection signal, dividing the output signal from said voltage-controlled oscillator, said prescaler being supplied with an electric power through said first switch, said first frequency divider being constituted by a main frequency divider and a swallow frequency divider, a frequency-division output signal being used as said first clock signal to be fed to respective clock terminals of said main frequency divider and said swallow frequency divider, a frequency-division output signal of said swallow frequency divider being fed back to said multi-modulus prescaler as said selection signal, a frequency-division output signal of said main frequency divider being fed to said phase comparator; and

a modulating circuit for modulating a level of said selection signal with a suitable signal during a period from immediately after switching on again of said electric power supply by said intermittent operation control signal till said zero-phase signal is first generated after switching on again of said electric power supply.