Integrated dual charge pump power supply and RS-232 transmitter/receiver

• US 4,777,577 A
• Filed: 11/09/1987
• Issued: 10/11/1988
• Est. Priority Date: 10/01/1985
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Bingham, David, Allen, Charles M.
• Primary Examiner(s): Salce, Patrick R.
• Assistant Examiner(s): JONES, JUDSON
• Application Number:
  US07/117,992
• Time in Patent Office: 337 Days
• Field of Search: 363/59, 363/60, 363/61, 307/109, 307/110, 307/284, 307/305, 307/567, 320/1
• US Class Current: 363/60
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the conduit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

Claims

1. A circuit, integratable on a single piece of semiconductor substrate material, for providing a bipolar voltage output at substantially double the voltage of a unipolar voltage input source, including:

first and second voltage input terminals,

first and second positive transfer capacitor connection terminals,

first MOS semiconductor switch means for selectively connecting said first voltage input terminal to said first positive transfer capacitor connection terminal and said second voltage input terminal to said second positive transfer capacitor connection terminal,

first and second positive reservoir capacitor connection terminals, said first positive reservoir capacitor connection terminal connected to a fixed voltage,

second MOS semiconductor switch means for selectively connecting said first voltage input terminal to said second positive transfer capacitor connection terminal and said first positive transfer capacitor connection terminal to said second positive reservoir capacitor connection terminal,

first and second negative transfer capacitor connection terminals,

third MOS semiconductor switch means for selectively connecting said second voltage input terminal to said first negative transfer capacitor connection terminal and said second positive reservoir capacitor connection terminal to said second negative transfer capacitor connection terminal,

first and second negative reservoir capacitor connection terminals, said first negative reservoir capacitor connection terminal connected to a fixed voltage,

fourth MOS semiconductor switch means for selectively connecting said first negative transfer capacitor connection terminal to said second negative reservoir capacitor connection terminal and said second negative transfer capacitor connection terminal to said second voltage input terminal, and

selection means, coupled to said first, second, third and fourth semiconductor switch means, for selectively activating said first, second, third and fourth semiconductor switch means.

2. The circuit of claim 1 further including at least two RS-232 transmitter circuit, disposed in said semiconductor substrate material, having positive, negative and ground potential power conductors connected to said second positive reservoir capacitor terminal, said second negative reservoir capacitor connection terminal, and said second voltage input terminal, respectively, a data input connection terminal connected to said transmitter circuit for providing data to said transmitter circuit, and a data output terminal connection for providing an output from said transmitter circuit.

3. The circuit of claim 1 further including at least one RS-232 receiver circuit disposed on said semiconductor substrate material, including positive and ground power connection terminals connected to said first and second voltage input terminals and having a data input connection terminal and a data output connection terminal.

4. The circuit of claim 1 further including means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.

5. The circuit of claim 4 wherein said means is an inherent NPN transistor having multiple collectors.

6. The circuit of claim 4 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

7. The circuit of claim 6 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.

14. The circuit of claim 2 further including means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.

16. The circuit of claim 2 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

17. The circuit of claim 2 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.

18. The circuit of claim 3 further including means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.

19. The circuit of claim 18 wherein said means is an inherent NPN transistor having multiple collectors.

20. The circuit of claim 3 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

21. The circuit of claim 3 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.

22. The circuit of claim 1 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

23. The circuit of claim 1 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.

8. A circuit, intergratable on a single piece of semiconductor substrate material, for providing a bipolar voltage output at substantially double the voltage of a unipolar voltage input source, including:

first and second voltage input terminals,

first and second positive transfer capacitor connection terminals,

a first set of MOS semiconductor switches, including a switch connected between said first voltage input terminal and said first positive transfer capacitor connection terminal and a switch connected between said second voltage input terminal and said second positive transfer capacitor connection terminal,

first and second positive reservoir capacitor connection terminals, said first positive reservoir capacitor connection terminal connected to a fixed voltage,

a second set of MOS semiconductor switches, including a switch connected between said first voltage input terminal and said second positive transfer capacitor connection terminal, and a switch connected between said first positive transfer caapacitor connection terminal and said second positive reservoir capacitor connection terminal,

first and second negative transfer capacitor connection terminals,

a third set of MOS semiconductor switches, including a switch connected between said second voltage input terminal and said first negative transfer capacitor connection terminal and a switch connected between said second positive reservoir capacitor connection terminal and said second negative transfer capacitor connection terminal,

first and second negative reservoir capcitor connection terminals, said first negative reservoir capacitor connection terminal connected to a fixed voltage,

a fourth set of MOS semiconductor switches, including a switch connected between said first negative transfer capacitor connection terminal and said second negative reservoir capacitor connection terminal and a switch connected between said second negative transfer capacitor connection terminal and said second voltage input terminal,

selection means, coupled to said first, second, third and fourth set of semiconductor switches, for selectively activating said first, second, third and fourth sets of semiconductor switches.

9. The circuit of claim 8 further including at least one RS-232 transmitter circuit, disposed in said semiconductor substrate material, having positive, negative and ground potential power conductors connected to said second positive reservoir capacitor terminal, said second negative reservoir capacitor connection terminal, and said second voltage input terminal, respectively, a data input connection terminal connected to said transmitter circuit for providing data to said transmitter circuit, and a data output terminal connection for providing an output from said transmitter circuit.

10. The circuit of claim 8 further including at least one RS-232 receiver circuit disposed on said semiconductor substrate material, including positive and ground power connection terminals connected to said first and second voltage input terminals and having a data input connection terminal and a data output connection terminal.

11. The circuit of claim 8 further including means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.

12. The circuit of claim 11 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

13. The circuit of claim 12 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.

15. The circuit of claim 9 wherein said means is an inherent NPN transistor having multiple collectors.

24. The circuit of claim 9 further including means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.

25. The circuit of claim 24 wherein said means is an inherent NPN transistor having multiple collectors.

26. The circuit of claim 9 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

27. The circuit of claim 9 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.

28. The circuit of claim 10 further including means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material.

29. The circuit of claim 28 wherein said means is an inherent NPN transistor having multiple collectors.

30. The circuit of claim 10 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

31. The circuit of claim 10 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appering on said first voltage input terminal.

32. The circuit of claim 8 further including means for clamping said second negative reservoir capacitor connection terminal to a voltage no more positive than a voltage approximately equal to the voltage appearing on said second voltage input terminal.

33. The circuit of claim 8 further including means for clamping said second positive reservoir capacitor terminal to a voltage no more negative than a voltage approximately equal to the voltage appearing on said first voltage input terminal.