Complex arithmetic unit

• US 4,779,218 A
• Filed: 09/04/1985
• Issued: 10/18/1988
• Est. Priority Date: 09/04/1985
• Status: Expired due to Fees

• Current Assignee: Jeremy P. Jauch
• Original Assignee: Jeremy P. Jauch
• Inventors: Jauch, Jeremy P.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Shaw, Dale M.
• Application Number:
  US06/772,962
• Time in Patent Office: 1,140 Days
• Field of Search: 364/736, 364/754, 364/761, 364/768, 364/765
• US Class Current: 708/520
• CPC Class Codes: G06F 7/4806 Computations with complex numbers

Abstract

A complex arithmetic unit (CAU) for manipulating digital data representative of complex numbers. The CAU receives control signals and digital data representative of the real and imaginary parts of the complex operands from a host computer, and performs division, magnitude, and multiplication operations. The CAU has an input port for receiving input data and control signals; an output port for transferring output data and control signals; a RAM for storing input data, output data, and the results of intermediate calculations, the RAM having an input bus connected to the input port and an output bus connected to the output port; a data buffer for transferring digital data from the output bus; a controllable multiplier which also performs addition and subtraction of products, with an input connected to the input bus and the buffer, and an output for transferring digital output data; a parallel scaling multiplexer which receives the multiplier output data and extracts a selected contiguous subset of digital bits to scale the multiplier output data according to a predetermined scaling factor; an address multiplexer for extracting predetermined aspects of the multiplier output data; a lookup PROM addressable in response to the address multiplexer for storing approximate results of mathematical operations and transferring the results to the data buffer means and the multiplier input; a control device responsive to predetermined aspects of the multiplier output data extracted by the data scaling multiplexer control device and the address multiplexer, for controlling the other components.

Claims

1. A digital device for performing at least one type of mathematical operation on complex numbers by digitally manipulating digital input data which represent such numbers, comprising:

(a) data input means for receiving digital input data representative of complex numbers for digital manipulation and for transmitting said data over an input bus;

(b) data output means for transmitting digital output data, which represent the results of said mathematical operations, from an output bus to a destination device, said output data resulting from said digital manipulation of said input data;

(c) first data storage means for storing said input data, said output data, and intermediate digital data resulting from said digital manipulation, said first storage means being connected to said inut bus and to said output bus;

(d) data buffer means connected to said output bus for transferring digital data from said output bus to a multiplier I/O bus;

(e) arithmetic means for performing multiplication, addition of products, and subtraction of products, on digital data, having a first input means for receiving digital data from said input bus and a second input means for receiving digital data from said buffer means, and having output means for transferring digital output data resulting from said multiplication, addition, and subtraction;

(f) address multiplexer means connected to said output means of said arithmetic means for extracting a first portion of said output data of said arithmetic means;

(g) data scaling multiplexer means connected to said output means of said arithmetic means and to said input bus for extracting a second portion of said output data of said arithmetic means and transferring said second portion to said input bus, said second portion constituting output data or intermediate digital data;

(h) second data storage means addressable with the first portion of output data extracted by said address multiplexer means for storing digital data which represent approximate results of mathematical operations and for transferring said stored data that is addressed to said data buffer means; and

(i) control means responsive to said output data of said arithmetic means extracted by said data scaling multiplexer means and said address multiplexer means, for generating digital control signals to control said data input means, said first data storage means, said data buffer means, said arithmetic means, said data scaling multiplexer means, said address multiplexer means, and said second data storage means to perform said mathematical operations.

2. A device as in claim 1, wherein said output data transferred from said arithmetic means has a 16-bit least significant output portion, and a 16-bit most significant output portion.

3. A device as in claim 2, wherein said address multiplexer means includes:

(a) a zero detector for detecting and indicating by means of a zero signal whether the upper byte of the data from said most significant output is zero, and

(b) a lookup address multiplexer which receives said zero signal and in response thereto selects between a selected upper portion of a selected lower portion the most significant output as lookup address data for addressing said second data storage means

4. A device as in claim 3, wherein said zero signal is used by said address multiplexer means to select the most significant non-zero byte for use as address data to said second data storage means.

5. A device as in claim 2, wherein said data scaling multiplexer means includes a parallel data scaling register for receiving said arithmetic means output data, scaling same by a selected scale factor by extracting in parallel a selected subset of contiguous data bits therefrom, and transferring said selected data bits to said input bus.

6. A device as in claim 5, wherein said scale factor is selected in response to the digital value of the arithmetic means output data and the type of mathematical operation being performed.

7. A device as in claim 6, wherein said scale factor is selected in response to whether the upper byte of said arithmetic means output data is zero.

8. A device as in claim 6, further comprising latch means that record the value of the selected scale factor.

9. A device as in claim 1, wherein said control means includes third data storage means for storing, control data related to the type of mathematical operation being performed, and control logic means responsive to said stored control data for generating additional such digital control signals.

10. A device as in claim 9, wherein additional such digital control signals including external timing signals are received by at least one of said data input means and said data output means from an external source.

11. A device as in claim 10, further comprising internal clock means for generating internal timing signals,

wherein said control means generate such above-mentioned digital control signals in response to such internal timing signals, at times other than while digital input data are being received by said data input means, and

wherein said control means are timed, while digital input data are being received by said data input means, by such external timing signals.

15. The device of claim 1 further comprising a second data buffer means connected to said output bus for transferring digital data from said output bus to said input bus.

12. A device as in claim 12, wherein such timing of said control means by such internal timing signals has a greater rate than the rate of such timing by such external timing signals.

13. A device as in claim 12, wherein

such external timing signals are received by said internal clock means and include rising and falling edges,

each of such edges of such external timing signals causes said internal clock means to generate at least one internal timing signal having both a rising edge and a falling edge,

whereby timing by such internal timing signals has at least double the frequency of timing by such external timing signals.

14. A device as in claim 12, wherein

mathematical operations are performed by said above-mentioned components controlled by said control means while said control means are being timed by such external timing signals, and while digital input data are being received by said data input means.

16. A digital device for performing at least one type of mathematical operaton on complex numbers by digitally manipulating digital input data which represent such numbers comprising:

(a) first data storage means for storing said digital input data, output data which represents the results of said mathematical operations, and intermediate data resulting from said digital manipulation,

(b) data input means connected to said first data storage means for transferring said input data from a source device to said first data storage means,

(c) data output means connected to said first data storage means for transferring said output data from said digital device to a destination device,

(d) an arithmetic unit comprising;

input means for receiving digital data for manipulation,

multiplier means for performing multiplication on digital data received by said input means,

subtraction means for performing subtraction of products output by said multiplier means,

addition means for performing addition of products output by said multiplier means, and

output means for transferring digital output data resulting from said multiplication, subtraction, and addition,

(e) an address multiplexer means connected to said output means of said arithmetic means for extracting a first portion of said arithmetic unit output data,

(f) data scaling means connected to said output means and said input means of said arithmetic unit and to said first data storage means for extracting a second portion of said output data of said arithmetic unit and for transferring said second portion to said arithmetic unit input means and to said first data storage means, said second portion constituting said output data and said intermediate data,

(g) a second data storage means addressable with the first portion of output data extracted by to said address multiplexer means, for storing digital data which represent approximate results of mathematical operations and for transferring said stored data that is addressed to said arithmetic unit input means, and

(h) control means responsive to said arithmetic unit output data for generating digital control signals to control said data nput means, said first data storage means, said arithmetic unit, said data scaling multiplexer means, said address multiplexer means, and said second data storage means to perform said mathematical operations.

17. ln a device comprising an arithmetic means, a read/write memory for storing input data and intermediate calculations, a scaling means and a second memory for storing data, a method of performing complex division in which a numerator Nr+jNi is provided by a denominator Dr+jDi to produce a quotient Qr+jQi comprising the steps of:

providing in said second memory a lookup table that provides starting approximations LU of the reciprocal of a denominator D,

providing to said arithmetic means the values Nr, Ni, Dr, Di,

calculating in said arithmetic means a value NrQ=Nr*Dr+Ni*Di, scaling the value NrQ in said scaling means by an amount that varies with the magnitude of NrQ and storing the scaled value in said read/write memory,

calculating in said arithmetic means a denominator D=Dr*Dr+Di*Di, and scaling the value D by an amount which varies with the magnitude of D,

using the scaled value of D to obtain from said lookup table a starting approximation LU of the reciprocal of the denominator D,

calculating a value 1/D₂ =(LU*K1-LU² *D*K2) where K1 and K2 are scaling factors,

calculating a value 1/D₃ =1/D₂ *K1-(1/D₂)² *DK2) and storing the value 1/D₃ in said read/write memory,

multiplying in said arithmetic means the scaled value of NrQ and 1/D₃ and scaling the value to produce Qr,

calculating in said arithmetic means NiQ=Ni*Dr-Nr*Qi and scaling the value NiQ by an amount that varies with the magnitude of NiQ, and

multiplying the scaled value of NiQ and 1/D₃ and scaling the value to produce Qi.

18. In a device comprising an arithmetic means, a read/write memory for storing input data and intermediate calculations, and a second memory for storing data, a method of calculating the magnitude of a complex quantity L+jS or S+jL where L is the larger value and S the smaller value comprising the steps of

providing in said second memory a lookup table that provides estimates of the quantity M/L=(1+S² /L²)^1/2 for discrete values of S/L where 0≦

S/L≦

1,

storing in said read/write memory at least the value L,

providing to said arithmetic means the values L and S of the complex quantity whose magnitude is to be determined,

calculating in said arithmetic means the value of the ratio S/L,

using the value of S/L to obtain from said lookup table a value of the expression M/L=(1+S² /L²)^1/2, and

multiplying L and the value M/L to produce the value M=(L² +S²)^1/2.

19. In a device comprising an arithmetic means, a read/write memory for storing input data and intermediate calculations, and a second memory for storing data, a method of pe5rforming complex division in which a numerator Nr+jNi is divided by a denominator Dr+jDi to produce a quotient Qr+jQi comprising the steps of:

providing in said second memory a lookup table that provides starting approximations LU of the reciprocal of a denominator D,

providing to said arithmetic means the values Nr, Ni, Dr, Di,

calculating in said arithmetic means a value NrQ=Nr*Dr+Ni*Di, and storing the value in said read/write memory,

calculating in said arithmetic means a denominator D=Dr*Dr+Di*Di,

using the value of D to obtain from said lookup table a starting approximation LU of trhe reciprocal of the denominator D,

calculating a value 1/D₂ =(LU*K1-LU² *DK2) where K1 and K2 are scaling factors,

calculating a value 1/D₃ =1/D₂ *K1-(1/D₂)² *D*K2) and storing the value 1/D₃ in said read/write memory,

multiplying in said arithmetic means the value of NrQ and 1/D₃ to produce Qr,

calculting in said arithmetic means NiQ=Ni*Dr-Nr*Qi, and

multiplying the value of NiQ and 1/D₃ to produce Qi.