Method for successive alignment of chip patterns on a substrate

• US 4,780,617 A
• Filed: 10/03/1986
• Issued: 10/25/1988
• Est. Priority Date: 08/09/1984
• Status: Expired due to Term

• Current Assignee: Nikon Corporation
• Original Assignee: Nippon Kotsu Kabushiki Kaisha (Nikon Corporation)
• Inventors: Suzuki, Hiroyuki, Umatate, Toshikazu
• Primary Examiner(s): Westin, Edward P.
• Application Number:
  US06/915,027
• Time in Patent Office: 753 Days
• Field of Search: 250/548, 250/557, 250/237 R, 356/399, 356/400, 356/401, 364/559, 364/490, 364/491
• US Class Current: 250/548
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 9/7003 Alignment type or strategy, e.g. leveling, global alignment

Abstract

A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate to a reference position comprises moving the substrate so as to successively make selected chip patterns correspond to the reference position in accordance with design data representative of the positions of the selected chip patterns, measuring the positions of the selected chip patterns when made to correspond to the reference position, determining on the basis of the measured positions, coefficients of an operational equation so that the sum of the square of deviations between positions of the selected chip patterns determined by use of the operational equation and positions of the selected chip patterns represented by design data may be minimum, determining positions corresponding to the plurality of chip patterns on the basis of the operational equation, and moving the substrate in accordance with the determined positions.

Claims

1. A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate in accordance with predetermined coordinates to a reference position, comprising the steps of:

(a) moving said substrate so as to successively make selected several of said plurality of chip patterns correspond to said reference position in accordance with design data representative of the coordinates position of each of said plurality of chip patterns;

(b) measuring the positions of said selected several chip patterns when made to correspond to said reference position;

(c) determining, on the basis of the measured positions, coefficients of an operational equation so that the sum of the square of deviations between positions of said selected chip patterns determined by use of the operational equation and positions of said selected chip patterns represented by said design data may be minimum;

(d) determining positions corresponding to said plurality of chip patterns on the basis of said operational equation; and

(e) moving said substrate in accordance with said determined positions.

3. A method according to claim 1, wherein said coefficients include a first parameter dependent upon the rotation error of said substrate relative to said predetermined coordinates, the movement error of said substrate relative to a reference direction and the linear expansion and contraction of said substrate, and a second parameter dependent upon the offset of said substrate relative to said reference position.

2. A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate to a reference position, each of said plurality of chip patterns having reference mark means provided in a determined positional relationship with the corresponding chip pattern, said method comprising the steps of:

(a) measuring deviations between positions of said plurality of chip patterns and design data representing positions of said plurality of chip patterns, respectively, by use of said reference mark means;

(b) detecting a chip pattern that has no mark means within a predetermined range from the position represented by said design data;

(c) determining, on the basis of said deviations corresponding to chip patterns of said plurality excepting the detected chip pattern, positions corresponding to said plurality of chip patterns including said detected chip pattern; and

(d) moving said substrate in accordance with the determined positions.

4. With respect to a plurality of substrates which are respectively provided for a plurality of chip patterns formed in a regular arrangement in accordance with design data, a method for successive alignment of each of said chip patterns to a reference position, comprising the steps of:

(a) with respect to each of the first to the m-th of said substrates, measuring actual positions of several chip patterns selected from said plurality of chip patterns;

determining on the basis of said measured positions respective values of a plurality of parameters in an operational equation for obtaining the regularity in arrangement of said chip patterns on the corresponding substrate;

determining on the basis of said design data and said values of said plurality of parameters the regularity in arrangement of said chip patterns; and

moving said substrate in accordance with said determined regularity; and

(b) with respect to each of the (m+1)th one and after of said plurality of substrates, measuring actual positions of several selected ones of said plurality of chip patterns;

determining on the basis of the last-mentioned measured positions a value of at least one parameter other than specified parameters of said plurality of parameters in said operational equation;

determining on the basis of said design data, the value of said at least one parameter and the values of said plurality of parameters determined in step (a) the regularity in arrangement of said chip patterns; and

moving said substrate in accordance with said determined regularity.

5. A method according to claim 4, wherein the values of the parameters determined in said step (a) are applied to respective values of said specified parameters so as to determine the regularity in arrangement of said chip patterns with respect to each of the substrates from the (m+1)th and after.

6. A method according to claim 4, wherein an alignment mark attached to each of said plurality of chip patterns is formed on each of said substrates and the positions of said several selected chip patterns are actually measured as deviation from said reference position of said alignment mark.

7. A method according to claim 4, wherein said plurality of parameters includes the rotation error in a surface of a substrate generated in the alignment of said substrate, the offset error corresponding to the shift in a direction of the surface, the scaling error due to the linear expansion and contraction of said substrate itself and the degree of orthogonality of the arrangement of the chip patterns on said substrate.

8. A method according to claim 7, wherein at least one parameter mentioned above for obtaining the regularity of the arrangement of said chip patterns with respect to each of said substrates from the (m+1)th and after includes said rotation error and said offset error.

9. A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate in accordance with predetermined coordinates to a reference position, comprising the steps of:

(a) measuring deviations between positions of several chip patterns selected from said plurality of chip patterns and design data representing positions of the selected chip patterns;

(b) determining on the basis of said deviations coefficients of an operational equation so that the sum of the sqaure of deviations between positions of said selected chip pattern determined by use of the operational equation and said design data may be minimum;

(c) determining positions corresponding to said plurality of chip patterns on the basis of said operational equation; and

(d) moving said substrate in accordance with the determined positions.

10. A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate in accordance with predetermined coordinates to a reference position, comprising the steps of:

(a) with respect to each of several block areas distributed over a surface of said substrate, measuring deviations between positions of several chip patterns selected from chip patterns arranged in the corresponding block area and design data representing positions of the selected several chip patterns;

(b) with respect to said each block area, determining on the basis of said deviations coefficients of an operational equation so that the sum of the square of deviations between positions of said selected chip patterns determined by use of the operational equation and said design data may be minimum;

(c) with respect to said each block area, determining positions corresponding to said chip patterns arranged in the corresponding block area on the basis of said operational equation; and

(d) moving said substrate in accordance with the determined positions.

11. A method according to claim 10, wherein said coefficients includes a first parameter dependent upon the rotation error of said substrate relative to said predetermined coordinates, the movement error of said substrate relative to a reference direction and the linear expansion and contraction of said substrate, and a second parameter dependent upon the offset of said substrate relative to said reference position.

12. A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate in accordance with predetermined coordinates to a reference position, comprising the steps of:

(a) measuring deviations between positions of several chip patterns selected from said plurality of chip patterns and design data representing positions of said several chip patterns;

(b) detecting from said several chip patterns a chip pattern that is arranged at a position deviated from said design data by an amount larger than a predetermined amount;

(c) with respect to chip patterns of said plurality excepting the detected chip pattern determining on the basis of said deviations coefficients of an operational equation so that the sum of the square of deviations between positions of said remaining chip patterns determined by use of the operational equation and said design data may be minimum;

(c) determining positions corresponding to said plurality of chip patterns including the detected chip pattern on the basis of said operational equation; and

(d) moving said substrate in accordance with the determined positions.

13. A method according to claim 12, wherein said coefficients include a first parameter dependent upon the rotation error of said substrate relative to said predetermined coordinates, the movement error of said substrate relative to a reference direction and the linear expansion and contraction of said substrate, and a second parameter dependent upon the offset of said substrate relative to said reference position.

14. A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate to a reference position, comprising the steps of:

(a) measuring deviations between positions of said plurality of chip patterns and design data representing positions of said plurality of chip patterns;

(b) detecting a chip pattern that is arranged at a position deviated from said design data by an amount larger than a predetermined amount;

(c) determining, on the basis of said deviations corresponding to chip patterns of said plurality excepting the detected chip pattern, positions corresponding to said plurality of chip patterns including said detected chip pattern; and

(d) moving said substrate in accordance with the determined positions.