Wait mode power reduction system and method for data processor

• US 4,780,843 A
• Filed: 10/13/1987
• Issued: 10/25/1988
• Est. Priority Date: 11/07/1983
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Tietjen, Donald L.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/107,899
• Time in Patent Office: 378 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

Claims

1. In a data processing system comprising:

data processor means for executing instructions and for responding to interrupt requests;

subsystem means for providing interrupt requests to said data processor;

interrupt mask means responsive to the execution of instructions by said data processor means for preventing sid data processor means for responding to interrupt requests from said subsystem means; and

clock means for supplying clocking pulses to said data processor means and said subsystem means;

a power reduction system comprising;

wait mode means responsive to a power-down signal received from said data processor means for reducing power consumption by the data processing system; and

clock stopping means responsive to said power-down signal for interrupting the supply of clocking pulses to said subsystem means only if said interrupt mask means is preventing said data processor means from responding to interrupt requests from said subsystem means.

2. A data processing system according to claim 1 further comprising:

monitor means for receiving clocking pulses from said clock means and for periodically resetting said data processing means; and

monitor control means responsive to the execution of instructions by said data processing means for preventing said monitor means from resetting said data processing means; and

wherein;

said clock stopping means is further responsive to said power-down signal for interrupting the supply of clocking pulses to said monitor means only if said monitor control means is preventing said monitor means from resetting said data processing means.

3. A data processing system according to claim 1 wherein said subsystem means further comprises:

monitor means for periodically resetting said data processor means; and

monitor control means responsive to the execution of instructions by said data processing means for preventing said monitor means from resetting said data processing means; and

wherein;

said clock stopping means is further responsive to said monitor control means to interrupt the supply of clocking pulses to said subsystem means only if said monitor control means is preventing said monitor means from resetting said data processing means.