Priority arbitration circuit for processor access

• US 4,787,032 A
• Filed: 09/08/1986
• Issued: 11/22/1988
• Est. Priority Date: 09/08/1986
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Culley, Paul R.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US06/905,075
• Time in Patent Office: 806 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/240
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/285 Halt processor DMA G06F13/30 takes precedence

Abstract

A personal computer is disclosed having a microprocessor RESET/HOLD arbitration circuit and logic. The RESET/HOLD arbitration circuit requires a RESET signal to wait until any pending microprocessor "HOLD" is serviced or in the alternative and in the event the "RESET" signal is being processed causes the microprocessor "HOLD" signal to wait. The priority arbitration circuit and logic is essential to the proper operation of the 80386 microprocessor particularly in shifting from the "protected" mode of the microprocessor to the "real" mode of the microprocessor, since many third party application programs require the use of the microprocessor "protected" mode and require that the microprocessor be "reset" before returning to the "real" mode. The microprocessor "reset" must be accomplished by resetting the microprocessor without resetting the entire machine and without losing a HOLD request during the RESET. The computer system must also be capable of retaining a RESET request while either a DMA or REFRESH cycle is processed.

Claims

1. A personal computer with a high speed microprocessor compatible with applications software written for slower speed microprocessors comprising:

(a) a high speed microprocessor with a real and protected mode electrically coupled to a high speed data bus;

(b) non-volatile memory electrically coupled to a slow speed data bus;

(c) bus controller electrically coupling the high speed data bus to the slow speed data bus;

(d) dynamic memory electrically coupled to the high speed data bus;

(e) at least one input/output device coupled to said slow speed data bus;

(f) first microprocessor instruction halting means responsive to dynamic memory refresh cycle, said cycle repeatably occurring at timed intervals to generate a first microprocessor hold request;

(g) second microprocessor instruction halting means responsive to a direct memory access (DMA) request to generate a second microprocessor hold request;

(h) first arbitration means to arbitrate said first microprocessor hold request and said second microprocessor hold request to generate an arbitrated microprocessor hold request;

(i) switching means for switching the microprocessor from the real to protected mode and from protected to real mode, said switching means generates a microprocessor reset cycle when the microprocesor returns from the protected mode to the real mode; and

(j) detection means to detect the occurrence of an arbitrated microprocessor hold request during a microprocessor reset cycle to retain, for execution at a later time, the arbitrated microprocessor hold request generated during the execution of a microprocessor reset cycle.

2. The personal computer set forth in claim 1 wherein the detection means further detects and retains a microprocessor reset instruction, for execution at a later time, in the event an arbitrated microprocessor hold request is being processed at the time a microprocessor reset instruction is received.

3. The personal computer set forth in claim 2 further comprising a second arbitration logic means which arbitrates the priority of the microprocessor refresh cycle and the arbitrated microprocessor hold requests.

4. The personal computer set forth in claim 3 wherein said second arbitration logic means executes the microprocessor refresh cycle and arbitrated microprocessor hold requested in the order received.

5. A personal computer with a high speed microprocessor comprising:

(a) a high speed microprocessor with a real and protected mode electrically coupled to a data bus;

(b) non-volatile memory electrically coupled to a data bus;

(c) dynamic memory electrically coupled to the data bus;

(d) at least one input/output device;

(e) microprocessor instruction halting means responsive to dynamic memory refresh cycle, said cycle repeatably occurring at timed intervals to generate a first microprocessor hold request;

(f) microprocessor instruction halting means responsive to a direct memory access (DMA) request to generate a second microprocessor hold request;

(g) arbitration means to arbitrate said first microprocessor hold request and said second microprocessor hold request to generate an arbitrated microprocessor hold request;

(h) switching means for switching the microprocessor from the real to protected mode and from protected to real mode, said switching means generates a microprocessor reset cycle when the microprocessor returns from the protected mode to the real mode; and

(i) detection means to detect the occurrence of an arbitrated microprocessor hold request during a microprocessor reset cycle to retain, for execution at a later time, the arbitrated microprocesor hold request generated during the execution of a microprocessor reset cycle.

6. The personal computer set forth in claim 5 wherein the detection means further detects and retains a microprocessor reset instruction, for execution at a later time, in the event an arbitrated microprocessor hold request is being processed at the time a microprocessor reset instruction is received.