Random access memory apparatus

• US 4,794,566 A
• Filed: 02/10/1987
• Issued: 12/27/1988
• Est. Priority Date: 02/25/1986
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Richards, John W., Allsop, Derek P.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/013,233
• Time in Patent Office: 686 Days
• Field of Search: 365/189, 365/230, 365/233
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

A random access memory apparatus suitable for sequential write/non-sequential read, for example in a digital video special effects unit, comprises a write enable demultiplexer and a write address generator for demultiplexing incoming data into N channels A to D, where N is at least two, N memories in each of the N channels A to D, the incoming data allocated to any given one of the channels A to D being written into all of the memories in the given channel A to D, a read address generator for reading stored data from any one of the memories and, on reading from a memory, setting a busy flag for that memory, the busy flag being cleared N data periods later, and a busy flag control to control the read address generator to step onto a different memory in the same channel A to D as a memory to be read, when the memory to be read has a set busy flag. Apparatus is also provided for non-sequential write/sequential read and non-sequential write/non-sequential read.

Claims

1. A random access memory apparatus for processing data in successive sample periods, said apparatus comprising:

N memories in each of N channels, wherein N is at least two;

a busy flag memory;

a write enable demultiplexer for selectively supplying write enable signals to said memories;

a write address generator for writing incoming data into all of said memories in any given one of said channels under control of said write enable signals;

a read enable demultiplexer for selecting one of said channels;

a read address generator for reading stored data from any one of said memories in the selected channel and, on reading from said one memory, setting a busy flag corresponding thereto in said busy flag memory to mark said one memory as busy;

means to clear said busy flag N sample periods later; and

means responsive to said busy flag to control said read address generator to read from a memory in said one selected channel other than said one memory.

2. A random access memory apparatus according to claim 1 wherein N is equal to four.

3. A random access memory apparatus for processing data in successive sample periods, said apparatus comprising:

N memories in each of N channels, where N is at least two and each memory has a plurality of memory locations;

a busy flag memory;

a write enable demultiplexer for selectively supplying write enable signals to said memories;

a write address generator for writing incoming data designated by said demultiplexer for any given one of said channels, into one of said memories in said given channel and, on writing into said one memory, setting a busy flag corresponding thereto in said busy flag memory to mark said one memory as busy, and, when said one memory has a set busy flag corresponding thereto, stepping on to another of said memories in said given channel until reaching a memory corresponding to which no set busy flag is found;

means to clear said busy flag N sample periods later;

respective additional memory means associated with each of said memories for storing valid data flags respectively associated with each memory location in which data has been written;

means to clear each of said valid data flags when said data is cleared from the associated memory location;

a read enable demultiplexer for selecting a particular memory in a channel in dependence on said valid data flags; and

a read address generator for reading stored data from any of said memories and, on reading from a given memory location in a particular one of said channels, deriving the data from one of said memories in said particular channel which has a valid data flag associated with said given memory location.

4. A random access memory apparatus according to claim 3 further comprising:

an OR gate for combining said valid data flags into a key signal to indicate the presence or absence of valid video data in any of said memory locations;

a selector controlled by said OR gate to switch between data read from one of said memory locations and an alternative data source.

5. A random access memory apparatus according to claim 3 wherein N is equal to four.