Self-aligned split gate eprom process

CAFC
  • US 4,795,719 A
  • Filed: 08/22/1986
  • Issued: 01/03/1989
  • Est. Priority Date: 05/15/1984
  • Status: Expired due to Term
First Claim
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1. A method of manufacturing a memory cell containing a split gate transistor comprising:

  • forming first polycrystalline silicon on, but separated from a semiconductor substrate by first insulation, said first polycrystalline silicon defining a floating gate having a first edge and a second edge opposite said first edge;

    forming a photoresist pattern over said substrate and over a surface of said first polycrystalline silicon, said surface extending laterally between the first and second edges, a first opening being formed in said photoresist pattern to expose both the first edge of said floating gate and a first portion of the semiconductor substrate extending laterally from said first edge and a second opening being formed in said photoresist pattern to expose a second portion of the semiconductor substrate laterally spaced apart from said floating gate;

    implanting selected impurities into those portions of the semiconductor substrate exposed by the openings of said photoresist thereby to form a source region laterally spaced apart from said floating gate and a drain region extending from but self-aligned to the first edge of said floating gate.

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