Bus master having burst transfer mode

• US 4,799,199 A
• Filed: 09/18/1986
• Issued: 01/17/1989
• Est. Priority Date: 09/18/1986
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moyer, William C., Wilson, William D., Scales, Hunter L. III
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US06/908,766
• Time in Patent Office: 852 Days
• Field of Search: 365/230, 365/235, 365/238, 364/200, 364/900
• US Class Current: 365/230.08
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.

Claims

1. A bus master for use with a memory capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer, the bus master comprising:

address register means for selectively storing the selected access address, and for incrementing modulo m a predetermined set of n bits of the selected access address in response to an increment signal; and

controller means for initially providing the burst request signal to the memory in response to a burst start signal, and, for m times thereafter, providing the burst request signal to the memory and the increment signal to the address register means in response to concurrently receiving from the memory both a burst acknowledge signal and a termination signal.

2. The bus master of claim 1 wherein the controller means will provide neither the burst request signal nor the increment signal in response to receiving only the termination signal.

3. The bus master of claim 2 wherein n is Two (2) and m is Four (4).

4. The bus master of claim 2 wherein the set of n bits of the access address are selected to correspond to the size of the operands.

5. The bus master of claim 4 wherein n is Two (2) and m is Four (4).

6. The bus master of claim 1 wherein the set of n bits of the access address are selected to correspond to the size of the operands.

7. The bus master of claim 6 wherein n is Two (2) and m is Four (4).

8. The bus master of claim 1 wherein n is Two (2) and m is Four (4).