Method and device for recording analog parameters on a static digital memory

• US 4,807,179 A
• Filed: 04/09/1985
• Issued: 02/21/1989
• Est. Priority Date: 12/19/1984
• Status: Expired due to Fees

• Current Assignee: Etat Francais Represente Par Le Delegue General Pour L'Armement
• Original Assignee: Etat Francais
• Inventors: Lebrun, Dominic, Clere, Jean-Michel
• Primary Examiner(s): Kemeny, Emanuel S.
• Assistant Examiner(s): CLARK, DAVID
• Application Number:
  US06/721,480
• Time in Patent Office: 1,414 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 360/5, 371/12-14, 371/66
• US Class Current: 711/173
• CPC Class Codes: G07C 5/085 using electronic data carriers
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A method and apparatus are provided for data storage in, for example, a black box for an aircraft. A static digital memory is divided into three portions, A, B and C. Data is read into successive sequential portions of wrap-around memory portion A. When an interrupt signal is received, e.g., due to a crash, the memory part A address to which the last data was input is entered into memory part B, along with an indication of which parameter was entered at that address. Data then is stored in sequential portions of memory part C until the end thereof is reached. To read the data, the last address to which data was entered in part A is read from memory part B, data is read from the position immediately following that entry to the end of part A, then from the beginning of part A through to the last entry. Data then is read from memory part C. The resultant data represents a period of time from shortly before, e.g., 0.3 ms, to some time, e.g., a couple of seconds, after the interrupt signal.

Claims

1. A method for recording and retrieving variations over time of analog parameters in a static digital memory comprising:

allocating a memory into n memory blocks corresponding to n parameters, n being a positive integer, and allocating each block into first, second and third parts;

loading at a frequency f and cyclically storing values of m components representing each analog parameter in sequential portions of the first part of a respective memory block, m being a positive integer, and, if a last sequential portion of said first part of said respective memory block is reached, continuing storing the m components in said first part of said respective memory block by wrapping around to a first sequential portion of said first part of the respective memory block, and storing the m components in the first and subsequent sequential portions of said first part of the respective memory block;

detecting a starting signal;

upon detection of said starting signal, loading and storing in the second part of each memory block data including at least an address Ad of the last loaded sequential portion of the first part of the memory block before detection of the starting signal;

loading and storing at the frequency f, the m components in sequential portions of the third part of each memory block up to the last portion of the memory block;

retrieving recorded data by;

retrieving from the second part of each memory block the address Ad of the last stored sequential protion of the first part of each memory block;

retrieving data from the sequential portions of the first part of each memory block starting at an address Ad+1, and continuing up to the last sequential portion of said first part of each memory block;

retrieving data from the first portion of said first part of each memory block and from sequentially following portions of the first part of each memory block up to and including the address Ad retrieved from the second part of each memory block;

retrieving data from a first portion and sequentially following portions of the third part of each memory block up to a last sequential portion of each respective memory block.

2. A method according to claim 1, further comprising the step of generating said starting signal whenever at least one parameter value exceeds a predetermined threshold value for a predetermined time interval.

3. A method according to claim 1, further comprising the step of generating said starting signal with an external command signal.

4. The method according to claim 1, further comprising the step of generating said starting signal when each of a plurality of parameter values exceeds corresponding predetermined threshold values for predetermined time intervals.

5. The method according to claim 1, wherein said step of loading the second part of each memory block is performed just after detection of the starting signal and before a subsequent loading of data, the timing of said subsequent loading of data being determined by the frequency f.

6. The method according to claim 1, wherein the data stored in the second part of each memory includes:

a part of the address Ad of the portion of the first part of the memory block being addressed when the starting signal is detected;

the identity of the component stored at the address Ad and

the identity of the parameter allocated to the respective memory block.

7. The method according to claim 1, wherein m and n equal 3, and wherein the metho further comprises the steps of generating the starting signal when two of the components of any one of the parameters simultaneously exceed the corresponding threshold value for a predetermined time interval.

8. The method according to claim 6, wherein:

the address Ad comprises 12 bits, divided into four low order bits, four middle order bits and four high order bits;

the data loaded in the second part of a first memory block comprising eight bits including the four low order bits, two of said four low order bits identifying the component loaded at the address Ad of said first part of said first memory block and two of said low order bits identifying the parameter loaded in said first memory block;

the data loaded in the second part of the second memory block comprises eight bits including the four middle order bits, two of said middle order bits identifying the component loaded at the address Ad of said first part of said second memory block and two of said middle order bits identifying the parameter loaded in said second memory block; and

wherein the data loaded in the second part of the third memory block comprises eight bits including the high order bits, two of said four high order bits identifying the component loaded at the address Ad of said first part of said third memory block and two of said four high order bits identifying the parameter loaded in the third memory block.