Interactive programming and diagnostic system for use with implantable pacemaker

• US 4,809,697 A
• Filed: 10/14/1987
• Issued: 03/07/1989
• Est. Priority Date: 10/14/1987
• Status: Expired due to Term

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Siemens Pacesetter, Inc. (Abbott Laboratories Incorporated)
• Inventors: Snell, Jeffery D., Causey, James D. III, Schloss, Harold C.
• Primary Examiner(s): Jaworski, Francis J.
• Assistant Examiner(s): MANUEL, GEORGE C
• Application Number:
  US07/108,842
• Time in Patent Office: 510 Days
• Field of Search: 128/419 PT, 128/419 PG, 128/630, 128/631, 128/697, 128/903
• US Class Current: 607/31
• CPC Class Codes: A61N 1/37235 Aspects of the external programmer
• CPC Class Codes: Y10S 128/903 Radio telemetry

Abstract

An analyzer-programmer system (30) for use with an implantable medical device, such as a cardiac pacemaker (20). The system facilitates non-invasive communications with the implantable device and makes analysis of the operation of the implantable device easier to understand and perform. The system includes conventional processor means (42) for processing a sequence of stored instructions stored in programmable read-only memory, or ROM (40). The ROM, although designed to be accessed through predefined page of information, and blocks within such pages, is configured to allow in-page addressing within any of a plurality of pages in a linear fashion. Programmed intervals to be sent to the implantable device are displayed by the system in tabular form or as scaled time-lines or bars (FIG. 9A), with each separate interval beginning and ending in proper timed sequence, thereby providing a prediction of the expected performance. Such programmed intervals can overlay or sidelay measured performance (FIG. 9B), thereby facilitating a comparison between predicted and measured performance. The system also includes telemetry head means (28) for sending and receiving control and data signals to and from the implanted medical device ( 20). The telemetry head means (28) includes processing circuitry (FIG. 4C) that greatly simplifies the other circuitry needed in order to effectuate such communication.

Claims

1. An analyzer programmer system for controlling and monitoring an implantable programmable pacemaker, said pacemaker having means for receiving control signals and means for transmitting data signals, said analyzer programmer system comprising:

telemetry head means for noninvasively sending control signals to said pacemaker and for noninvasively receiving data signals form said pacemaker;

processing means coupled to said telemetry head means for generating said control signals in response to selected commands entered into said system, and for processing said data signals received from said telemetry head means;

memory means coupled to said processing means for storing said data signals; and

electronic display means for displaying the information contained within said data signals and said control signals, said display means including means for electronically displaying a plurality of graphically depicted programmed intervals, said graphically depicted programmed intervals including a graphical indication of the starting point and duration of selected time intervals included within a graphical representation of a predefined cycle associated with the operation of said programmable pacemaker, said selected time intervals being specified in the control signals sent to said pacemaker.

2. The analyzer programmer system of claim 1 wherein said control signals control at least the programmed duration of selected time intervals used during operation of said pacemaker, and said data signals include at least the measures duration of selected time intervals associated with the operation of said pacemaker, and further wherein the programmed intervals graphically displayed by said electronic display means comprise a scaled graphical diagram of predicted time intervals within said predefined pacemaker cycle that results from the sending of the control signals to said pacemaker and the acting upon said control signals by said pacemaker.

3. The analyzer programmer system of claim 2 wherein said display means further includes means for simultaneously displaying the programmed time intervals of said electronic display means and the measured time intervals derived form said data signals, thereby facilitating a comparison between that which is predicted and that which is measured.

4. A time interval programming system for controlling and monitoring an implantable pacemaker, said implantable pacemaker including means for receiving commands, said time interval programming system comprising:

means for transmitting commands to the receiving means of said implantable pacemaker, said commands including the programmed duration of selected time intervals associated with the operation of said implantable pacemaker; and

means for graphically displaying selected time intervals included in said commands in a visual representation that depicts when, within a graphical depiction of a predefined cycle associated with the operation of said implantable pacemaker, each displayed time interval begins and ends.

5. The time interval programming system of claim 4 wherein said implantable pacemaker further includes means for sensing and generating events, and means for transmitting data signals representative of said events, and wherein said time interval programming system further includes means for receiving said data signals, and wherein said graphical display means includes data display means for simultaneously displaying events sensed and generated by said implantable pacemaker in a timed relationship aligned with the display of said time intervals, said data display means showing the events thus displayed in timed relationship relative to said predefined cycle.

6. The time-interval programming system of claim 4 wherein the implantable pacemaker is a dual chamber pacemaker and wherein the time intervals displayed by said graphical display means include programmed atrial and ventricular refractory periods and a programmed A-V delay interval associated with the operation of the dual chamber pacemaker.

7. In an analyzer programmer system for use with an implantable pacemaker, said system including processing means for carrying out specific instructions associated with a particular type of implantable pacemaker;

a removable program cartridge wherein said specific instructions are stored;

a data bus connecting said processing means with said program cartridge, and over which data bus said specific instructions are transferred to said processing means from said program cartridge; and

an address bus, also connecting said processing means with said program cartridge, and over which address bus a data address signal is provided to said program cartridge from said processing means;

a memory access system within said program cartridge comprising;

multi-page memory means within said program cartridge for storing the specific instructions at one of a plurality of possible pages, said multi-page memory means including access means for accessing a specific location within said memory means that includes means for specifying a desired page where desired data is located, and means for subsequently specifying where on the desired page the desired data is located, whereby at least two consecutive instructions may be used to retrieve data from said multi-page memory means;

a first instruction to specify the page, and a second instruction to specify where on the specified page the desired data is located; and

decoding means responsive to the receipt of a single data address instruction received over said address bus for decoding said single data address instruction and for placing the data at the specific location designated by the decoded single data address instruction on said data bus for presentation to said processing means, said decoding means accomplishing its function of retrieving the addressed data without the need for consecutive plural instructions specifying first the page and second the location on the page where the data is located whereby data can be retrieved from said multi-page memory means using a single memory instruction.

8. The memory access system of claim 7 wherein said decoding means includes means for coupling a selected portion of said address bus directly to said data bus.

9. A memory access system for a read-only memory (ROM) subsystem of a microprocessor-controlled programmer system, said microprocessor-controlled programmer system being used for programming a medical device, said microprocessor-controlled programmer system having means for generating a clock signal, said clock signal defining a basic clock cycle, said clock signal being applied to said ROM subsystem to control the retrieval of data stored therein, said ROM subsystem including a plurality of commercially available ROM devices that have been programmed with specified data, said ROM devices being configured to organize the specified data into a plurality of pages, and said ROM devices typically requiring two consecutive memory instructions, executable over at least two consecutive basic clock cycles, in order to retrieve a selected portion of the specified data stored in said ROM devices:

a first instruction to specify a page, and a second instruction to specify where on the specified page the selected portion of the specified data is located;

the improvement of said memory access system comprising;

address means fo generating a single memory address instruction that specifies the location within said ROM where the selected portion of the specified data is stored;

means for applying said single memory address instruction to said ROM subsystem; and

decoding means within said ROM subsystem responsive to said single memory address instruction for retrieving the selected portion of the specified data from said ROM devices within a single basic clock cycle.

10. The memory access system of claim 9 wherein said decoding means comprises a programmed logic array (PAL) device that includes:

means for receiving a multi-bit address instruction; and

means responsive to the individual its of said multi-bit address instruction for immediately generating, without waiting for the beginning of the next basic clock cycle, a set of appropriate control signals that cause the selected portion of the specified data to be retrieved from said ROM devices.

11. A method of analyzing the ECG signals sensed by an implantable cardiac pacemaker, said pacemaker having a plurality of specified time intervals associated with its operation, said method comprising the steps of:

(a) sending control signals to said implantable cardiac pacemaker that indicate the duration of said specified time intervals;

(b) electronically displaying a first time-scaled graphical display that displays a representation of said specified time intervals in graphical form;

(c) receiving ECG signals from said cardiac pacemaker that indicate various cardiac events sensed by said pacemaker; and

(d) electronically displaying a second time-scaled graphical display that graphically displays the occurrence of said sensed cardiac events.

12. The analyzing method of claim 11 wherein the electronic first and second time-scaled displays are displayed simultaneously, thereby facilitating a comparison of the specified time intervals and the measured cardiac events.

13. The analyzing method of claim 11 wherein the specified time intervals displayed in said first time-scaled display include an A-V interval and a rate interval.

14. The analyzing method of claim 11 wherein step (6) comprises displaying said specified time intervals as a horizontal bar chart, the horizontal axis of said bar chart comprising a time axis, each time interval being represented as a separate bar on said bar chart that begins and ends at an appropriate location along said horizontal axis.