Method of making an electrical multilayer copper interconnect

• US 4,810,332 A
• Filed: 07/21/1988
• Issued: 03/07/1989
• Est. Priority Date: 07/21/1988
• Status: Expired due to Fees

• Current Assignee: Microelectronics and Computer Technology Corporation
• Original Assignee: Microelectronics and Computer Technology Corporation
• Inventors: Pan, Ju-Don T.
• Primary Examiner(s): Tufariello, T. M.
• Application Number:
  US07/222,486
• Time in Patent Office: 229 Days
• Field of Search: 204/15, 204/38.1, 204/38.4, 204/40
• US Class Current: 205/125
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H05K 2201/0154 Polyimide
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0577 Double layer of resist having the same pattern
• CPC Class Codes: H05K 2203/0585 Second resist used as mask for selective stripping of first resist
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4647 by applying an insulating layer around previously made via studs

Abstract

A method of making an electrical multilayer copper interconnect in which the electrical lines are protected by an electroplated overcoat. A plating interconnect is deposited on a substrate, a sacrificial layer of dielectric material is deposited on the plating interconnect. Thereafter a plating mask is formed on the dielectric material. Two self-aligned plating masks are patterned in one step, one of which is a plating mask for copper plating and the other is a plating mask for the overcoat. Preferably, before electroplating the overcoat, the copper is etched for exposing the sides adjacent the dielectric layer for allowing overcoating all of the copper.

Claims

1. A method of making an electrical multilayer copper interconnect comprising,

depositing a plating interconnect on a substrate,

depositing a sacrificial layer of dielectric material on the plating interconnect,

forming a plating mask on the dielectric material,

etching away the dielectric material through the plating mask,

plating a copper conductor into the etched away dielectric,

stripping away the plating mask,

forming a pillar plating mask on top of the conductor,

plating a copper pillar onto the conductor,

stripping the pillar plating mask,

electroplating an overcoat layer on the exposed surface of the copper pillar and conductor, and

stripping the sacrificial dielectric layer.

2. The method of claim 1 including,

before electroplating the overcoat, etching the copper for exposing the sides adjacent to the dielectric layer for allowing overcoating all of the copper.

3. The method of claim 1 wherein the dielectric material is polyimide.

4. The method of claim 1 including stripping the plating interconnect below the stripped dielectric layer.

5. The method of claim 1 wherein the overcoat is from a group consisting of nickel and chromium.

6. The method of claim 1 wherein the dielectric material is resistant to the stripping of the plating mask.

7. A method of making an electrical multilayer copper interconnect comprising,

depositing a plating interconnect on a substrate,

depositing a layer of polyimide on the plating interconnect,

forming a conductor plating mask on the polyimide,

patterning the conductor plating mask and the polyimide in a self-aligned pattern for a conductor,

electroplating a copper conductor into the pattern and connected to the interconnect,

stripping away the conductor plating mask,

forming a pillar mask on top of the conductor,

electroplating a copper pillar onto the conductor,

stripping the pillar plating mask,

etching away the copper sides adjacent the polyimide, and

electroplating an overcoat layer on the exposed surface of the copper pillar and conductor,

stripping the layer of polyimide away, and

stripping the plating interconnect below the stripped polyimide.