Stacked capacitor

• US 4,827,323 A
• Filed: 05/12/1988
• Issued: 05/02/1989
• Est. Priority Date: 01/07/1986
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tigelaar, Howard L., Riemenschneider, Bert R.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Featherstone, Donald J.
• Application Number:
  US07/195,346
• Time in Patent Office: 355 Days
• Field of Search: 357/23.6, 357/51, 357/55, 357/71, 361/311, 361/313
• US Class Current: 257/534
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates. The area etched away is then filled with a suitable dielectric and a contact is made to the unetched interleaved plates. Thus a fully interleaved capacitor is provided using relatively simple fabrication techniques while still providing increased capacitance.

Claims

1. An integrated circuit having a capacitor, said capacitor comprising:

a first plurality of conductive plates of a first conductive material, interleaved but insulated from a second plurality of conductive plates of a second conductive material different from said first conductive material;

a first electrical contact at the edge of said interleaved plates connected to said first plurality of conductive plates but insulated from said second plurality of conductive plates;

a second electrical contact at the edge of said interleaved plates connected to said second plurality of conductive plates but insulated from said first plurality of conductive plates; and

a separate, unitary dielectric plate between each interleaved pair of said first plurality of conductive plates and said second plurality of conductive plates.

2. An integrated circuit as in claim 1 wherein said dielectric plate is silicon dioxide.

3. The integrated circuit of claim 1 wherein:

said first and second conductive materials are selectively etchable relative to each other and to said dielectric material.

4. The integrated circuit of claim 1 further comprising:

a substrate having a cavity formed therein, wherein said capacitor is formed within said cavity.

5. An integrated circuit having a semiconductor substrate with a substantially flat surface oriented along a horizontal direction for forming circuit components thereon, said integrated circuit further including a capacitor, said capacitor comprising:

a plurality of first conductive plates vertically stacked above the substrate, each plate having a first edge for electrical connection;

a plurality of second conductive plates interleaved with the plurality of first conductive plates, each second plate including a second edge for electrical connection extending along the horizontal direction beyond the first conductive plates to form a recessed space adjacent each first conductive plate and between the second conductive plates, the first edge of each first plate extending along the horizontal direction beyond the second conductive plates to form a recessed space adjacent each second conductive plate and between the first conductive plates;

a plurality of separate, unitary dielectric layers positioned between the interleaved first and second plates;

insulating means positioned in the recessed spaces for electrically isolating the first edges from the second conductive plates and for electrically isolating the second edges from the first conductive plates;

first conductor means, formed along the first edges and insulated from the second conductive plates, for providing electrical contact between the first conductive plates; and

second conductor means, formed along the second edges and insulated from the first conductive plates, for providing electrical contact between the second conductive plates.

6. The integrated circuit of claim 5 wherein the first capacitor edges are substantially in vertical alignment with respect to the horizontal direction.

7. The integrated circuit of claim 6 wherein the first capacitor edges are aligned in a first plane transverse to the horizontal direction and the second capacitor edges are substantially in vertical alignment with respect to the horizontal direction forming a second plane parallel to the first plane.

8. The integrated circuit of claim 5 wherein said first and second conductor means further provide means for coupling said capacitor to other circuit components.

9. An integrated circuit having a capacitor, said capacitor comprising:

a semiconductor substrate having a cavity formed along a substantially flat surface;

a plurality of layered first conductive plates positioned in the cavity, each plate having a first edge for electrical connection with other first plates;

a plurality of layered second conductive plates interleaved with the plurality of first conductive plates, each second plate including a second edge for electrical connection, each second edge extending beyond the first conductive plates to form a recessed space adjacent a first plate and between the second conductive plates, the first edge of each first plate extending beyond the second conductive plates to form a recessed space adjacent a second plate and between the first conductive plates;

a plurality of separate, unitary dielectric layers positioned to insulate the interleaved first and second plates from one another;

insulating means positioned in the recessed spaces for electrically isolating the first edges from the second conductive plates and for electrically isolating the second edges from the first conductive plates;

first conductor means, formed along the first edges and insulated from the second conductive plates, for providing electrical contact between the first conductive plates; and

second conductor means, formed along the second edges and insulated from the first conductive plates, for providing electrical contact between the second conductive plates.

10. The integrated circuit of claim 9 wherein the first and second plate edges are substantially in parallel alignment with the substrate surface.

11. The integrated circuit of claim 9 wherein said first and second conductor means further provide means for coupling said capacitor to other circuit components.