Discrete cosine transform arrangement

• US 4,837,724 A
• Filed: 05/06/1987
• Issued: 06/06/1989
• Est. Priority Date: 05/12/1986
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Borgers, Stephanus M. C., Visser, Cornelis P.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Shaw, Dale M.
• Application Number:
  US07/047,795
• Time in Patent Office: 762 Days
• Field of Search: 364/725, 364/726, 358/133, 358/135
• US Class Current: 708/402
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence

Abstract

In a discrete cosine transformation (DCT) arrangement with an equivalent distribution between accuracy of intermediate results and the number of calculation operations to be performed, the group of N input samples is first subjected to a shuffle operation (903). Consequently, these input samples are applied to a combination circuit (90) in a sequence which is different from the sequence in which they are received. The combination circuit (90) supplies the sum and the difference of each two successive input samples. A selection circuit (91) continuously returns all sum samples except the last one to the input of the combination circuit. Each difference sample and the last sum sample is multiplied once in a multiplier (92) by one weighting factor from a group of weighting factors and the product samples obtained thereby are group-wise accumulated in an accumulator circuit (93), with each group supplying a transform coefficient.

Claims

1. An arrangement for real-time calculation of discrete cosine transformation coefficients of a group of N signal samples of a time-discrete input signal, comprising:

combination means receiving the signal samples as well as a number of auxiliary samples for adding and subtracting predetermined combinations of said signal samples and said auxiliary samples for generating sum and difference samples;

selection means receiving the sum and difference samples and supplying said auxiliary samples as well as transfer samples, the auxiliary samples being constituted by selected ones of the sum and difference samples and the transfer samples being comprised by the remaining sum and difference samples;

multiplication means receiving the transfer samples and multiplying each by only one weighting factor selected from a plurality of predetermined weighting factors for generating product samples; and

accumulator means receiving the product samples for accumulating given samples of said product samples for generating the coefficients.

2. An arrangement as claimed in claim 1, wherein the auxiliary samples are comprised by sum samples.

3. An arrangement as claimed in claim 1 further comprising shuffle means to which the N-signal samples are applied in a first sequence and which supplies these signal samples in a second sequence which corresponds to the combinations of samples to be added or to be subtracted.

4. An arrangement as claimed in claim 1 wherein the combination means comprises two memories for storing a first and a subsequent second sample, which samples are applied to an adder-subtractor circuit and are supplied by a selection circuit which receives signal samples and the auxiliary samples and which applies them selectively to the two memories.

5. An arrangement for real-time calculation of N inverse discrete cosine transformation signal samples of a time-discrete signal from a group of N discrete cosine transformation coefficients, comprising:

multiplication means receiving the coefficients and multiplying each by only one weighting factor selected from a plurality of predetermined weighting factors for generating product samples;

accumulator means receiving the product samples for adding each time given samples of said product samples together for generating accumulation samples;

combination means receiving the accumulation samples as well as a number of auxiliary samples for adding and subtracting predetermined combinations of said accumulation samples and auxiliary samples for generating sum and difference samples; and

selection means receiving the sum and difference samples and supplying said auxiliary samples as well as transfer samples, the auxiliary samples being comprised by selected ones of the sum and difference samples and the transfer samples being comprised by the remaining sum and difference samples.

6. An arrangement as claimed in claim 5 further comprising shuffle means to which the N-coefficients are applied in a first sequence and which supplies these coefficients in a second sequence which corresponds to the combinations of coefficients to be added or to be subtracted.

7. An arrangement as claimed in claim 5 wherein the combination means comprises two memories for storing a first and a subsequent second sample, said first and second samples being applied to an adder-subtractor circuit and being supplied by a selection circuit which receives the accumulation samples and the auxiliary samples and which applies them selectively to the two memories.