Buried gate JFET

• US 4,845,051 A
• Filed: 10/29/1987
• Issued: 07/04/1989
• Est. Priority Date: 10/29/1987
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Cogan, Adrian I.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/115,076
• Time in Patent Office: 614 Days
• Field of Search: 437/203, 437/29, 437/59, 437/78, 437/160, 156/643, 357/22
• US Class Current: 438/193
• CPC Class Codes: H01L 29/66416 Static induction transistors [SIT] with an active layer made of a group 13/15 material H01L29/66454
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate

Abstract

A process for manufacturing a JFET in accordance with our invention includes the steps of forming an N- layer (12) on an N+ substrate (10), and forming an N+ layer (14) on the N- layer. A plurality of trenches (19) are etched to extend through the N+ layer and through a portion of the N- layer. A layer of sidewall oxide (20) is grown along the vertical walls of the trenches. The trenches are then extended so that the sidewall oxide only covers a portion of the vertical walls of the trenches. A layer of P type polysilicon (22) is then deposited in the trenches and impurities are diffused from the P type polysilicon into a surrounding portion of the N- layer to thereby form a plurality of P type regions (23). The size of the depletion region between the P type regions and the N- layer is controlled by applying selected voltages to the P type polysilicon, thereby controlling the current through the resulting JFET.

Claims

1. A method for manufacturing a transistor comprising the steps of:

providing a structure comprising a first region of semiconductor material of a first conductivity type, a second region of semiconductor material of said first conductivity type formed on said first region, a third region of semiconductor material of said first conductivity type formed on said second region, the dopant concentration of said second region being less than the dopant concentration of said first and third regions;

forming a plurality of trenches, each trench extending through said third region and a portion of said second region;

forming insulating layers on at least a portion of the walls of said trenches, said insulating layers extending from the top of said trenches along at least a portion of the walls of said trenches;

depositing doped semiconductor material in said trenches, said doped semiconductor material having a second conductivity type opposite said first conductivity type, wherein a portion of said insulating layers extends above the surface of said third region and the surface of said doped semiconductor material;

diffusing impurities from said doped semiconductor material into the portion of said second region adjacent said doped semiconductor material, thereby forming a plurality of regions of said second conductivity type within said second region; and

depositing conductive material on the surface of said third region and said doped semiconductor material, said portion of said insulating layers having a contour preventing step coverage of said conductive material over said portion of said insulating layers.

2. The method of claim 1 wherein said doped semi-conductor material comprises polysilicon.

3. The method of claim 1 further comprising the step of forming an insulating layer on the bottom of said trenches prior to forming said doped semiconductor material to prevent downward diffusion of impurities from said doped semiconductor material into said second region.

4. The method of claim 1 wherein said step of depositing doped semiconductor material comprises the step of forming said doped semiconductor material on the surface of said structure and in said trenches and removing the portion of said doped semiconductor material on said surface of said structure and a portion of said doped semiconductor material in said trenches, thereby leaving a portion of said doped semiconductor material at the bottom of said trenches, said method further comprising the step of filling an upper portion of said trenches with a layer of material so that the resulting transistor has a planar top surface.

5. The method of claim 1 wherein said step of forming said trenches comprises the step of etching said trenches to a first depth, forming said insulating layers, and then extending said trenches to a second depth.

6. The method of claim 1 wherein said doped semiconductor material extends to the top of said trenches so that the resulting transistor is substantially planar.

7. The method of claim 1 wherein said conductive material is a metal.

8. Method of claim 1 further comprising the step of electrically contacting said doped semiconductor material in said trenches, said first region, and said third region, such that application of a gate voltage to said doped semiconductor material modulates current permitted to flow between said first and third regions.

9. A method for manufacturing a transistor comprising the steps of:

providing a structure comprising a region of semiconductor material having a top surface and a trench extending through said top surface and at least a portion of said region of semiconductor material, said trench having walls;

forming a layer of insulating material on at least a portion of the walls of said trench;

depositing semiconductor material into said trench; and

depositing conductive material on the device resulting from the previous steps, a first portion of said conductive material electrically contacting said region of semiconductor material, a second portion of said conductive material contacting said semiconductor material within said trench, said layer of insulating material separating said region of semiconductor material from said semiconductor material within said trench, said conductive material being deposited so that step coverage of said conductive material over said insulating material is prevented and so that said first portion does not electrically contact said second portion.

10. The method of claim 9 wherein a portion of said insulating material extends higher than the top surface of said region of semiconductor material and higher than the top surface of said semiconductor material in said trench, said portion of insulating material separating said first and second portions of said conductive material.

11. The method of claim 9 wherein said step of depositing semiconductor material comprises the step of substantially filling said trench with said semiconductor material.

12. Method of claim 9 further comprising the step of subjecting said region of semiconductor material and said semiconductor material in said trench to an etching process prior to said step of depositing conductive material so that a portion of said insulating material extends higher than the top surface of said semiconductor material in said trench and said region of semiconductor material.

13. A method for manufacturing a transistor comprising the steps of:

providing a region of semiconductor material of a first conductivity type having a top surface and a plurality of trenches formed therein, each trench extending through said top surface and a portion of said region of semiconductor material;

forming insulating layers on at least a portion of the walls of said trenches;

depositing doped semiconductor material in said trenches, said doped semiconductor material having a second conductivity type opposite said first conductivity type, a portion of said insulating layers extending past the top surface of said doped semiconductor material and said region of semiconductor material;

diffusing impurities from said doped semiconductor material into the portion of said region of semiconductor material adjacent said doped semiconductor material, thereby forming a plurality of regions of said second conductivity type within said region of semiconductor material, said plurality of regions serving as the gate of said transistor; and

depositing conductive material on the surface of said region of semiconductor material and said doped semiconductor material, said portion of said insulating layers having a contour preventing step coverage of said conductive material over said portion of said insulating layers.