Process for manufacture of a vertical DMOS transistor
First Claim
1. A process for making a semiconductive device comprising the steps of:
- preparing a silicon wafer of one conductivity type having opposed front and back surfaces;
forming over the front surface and insulated therefrom a patterned polysilicon layer suitable for use as a silicon gate electrode;
using the polysilicon layer as a mask for forming over the front surface a surface well having a conductivity type opposite said one type;
doping simultaneously with dopant ions of the type characteristic of the one-type a surface portion of said surface well, the polysilicon layer and the back surface of the water, which had been previously stripped of any polysilicon or oxide;
driving in said dopants to form a source region of the one conductivity type at the surface of the well region, leaving unconverted a channel portion and a body diode portion of the well region, and to increase the conductivity of the polysilicon layer and of the back surface; and
providing a source electrode contacting both the source region and the body diode portion and providing a drain electrode contacting the back surface.
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Accused Products
Abstract
A process for forming a vertical n-channel DMOS transistor uses a common deposition step to form a phosphorus-rich predeposit simultaneously over the polysilicon gate electrode, over a central surface portion of a p-well region and over the back surface drain region of the chip. This predeposit is followed by a common drive-in step to form an n-type source region within the p-well region, and to make the polysilicon gate electrode and the back surface more conductive. In addition, the process uses the source region contact mask as a shadow mask for anistropically etching a via hole in the source region so that the source metallization can also contact the p-well region and serve also as a shorting contact to the p-well.
136 Citations
7 Claims
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1. A process for making a semiconductive device comprising the steps of:
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preparing a silicon wafer of one conductivity type having opposed front and back surfaces; forming over the front surface and insulated therefrom a patterned polysilicon layer suitable for use as a silicon gate electrode; using the polysilicon layer as a mask for forming over the front surface a surface well having a conductivity type opposite said one type; doping simultaneously with dopant ions of the type characteristic of the one-type a surface portion of said surface well, the polysilicon layer and the back surface of the water, which had been previously stripped of any polysilicon or oxide; driving in said dopants to form a source region of the one conductivity type at the surface of the well region, leaving unconverted a channel portion and a body diode portion of the well region, and to increase the conductivity of the polysilicon layer and of the back surface; and providing a source electrode contacting both the source region and the body diode portion and providing a drain electrode contacting the back surface. - View Dependent Claims (2)
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3. A process for making a vertical DMOS transistor comprising the steps of:
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preparing a silicon wafer of one conductivity type with front and back surfaces; forming on the front surface a silicon oxide gate layer;
forming over said silicon oxide layer a patterned polysilicon layer suitable for use as a silicon gate electrode;forming in a portion of the front surface of the wafer a surface well of the opposite conductivity type using the patterned polysilicon gate as a mask; stripping the back surface of the wafer and the exposed surface of the well region of the gate oxide layer; exposing the silicon wafer to an ambient of dopants of the conductivity type predominant in the wafer simultaneously to form a source region of the one conductivity type at the surface of the well region, to dope the polysilicon layer to adapt it for use as the gate electrode, and to open the back surface of the wafer to facilitate the provision thereto of a drain electrode; and forming source and drain electrodes to the source region and the back surface of the bulk portion, respectively. - View Dependent Claims (4)
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5. In a process of making a DMOS transistor that comprises a source electrode that contacts both a central portion of a body diode portion of a well region of one conductivity type and an annular source region of the opposite conductivity type surrounding said central portion, the steps of:
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forming, on a first surface of a semiconductive wafer whose bulk is of one conductivity type, a well region of the opposite conductivity type that surrounds an island surface region which is of the one conductivity type and is useful as a source region; depositing an insulating layer over said first surface; depositing a masking layer over said insulating layer; forming an opening in the masking layer overlying a central portion of the island surface region; etching the insulating layer through the opening in the masking layer in a manner to undercut the masking layer and form an opening in the insulating layer of an area larger than the opening in the masking layer; etching the wafer through the openings in the masking and insulating layers to form a via through a central portion of said island surface region of an area substantially corresponding to the area of the opening in the masking layer, leaving exposed edge portions of the via; stripping the masking layer; and depositing a layer suitable for use as the source electrode over the insulating layer through the opening in the insulating layer and the via in the island surface region to contact both the island surface region at the exposed edges of the via and the underlying body diode portion of the well region through the via in the island surface region. - View Dependent Claims (6, 7)
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Specification