Semiconductor memory

• US 4,860,255 A
• Filed: 08/09/1988
• Issued: 08/22/1989
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Ikuzaki, Kunihiko, Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/230,046
• Time in Patent Office: 378 Days
• Field of Search: 365/189, 365/205, 365/230, 365/186, 365/190, 365/149
• US Class Current: 365/205
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at the cross point thereof, each memory cell having an address terminal connected to the corresponding word line which it is coupled to so that each word line is connected to the address terminal of only one memory cell, wherein each memory cell also has a data terminal connected to the corresponding data line which it is coupled to;

each said memory cell including a MISFET having a gate electrode coupled to said address terminal, a first electrode coupled to said data terminal and a second electrode coupled to a capacitor;

selecting means coupled to said plurality of word lines including means for selecting one memory cell from said plurality of memory cells and means for placing said plurality of memory cells in a non-selected state;

amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one memory cell from said plurality of memory cells by said selecting means, said sense amplifier comprising first and second circuits;

said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and an N-channel MISFET coupled on a source side of said cross-coupled N-channel MISFETs for controlling the differential amplification operation of said cross-coupled N-channel MISFETs;

said second circuit including a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and a P-channel MISFET coupled on a source side of said cross-coupled P-channel MISFETs for controlling the differential amplification operation of said cross-coupled P-channel MISFETs;

means for supplying first and second timing signals to gates of said controlling N-channel and P-channel MISFETs, respectively, so that the differential amplification operation of said cross-coupled N-channel MISFETs is started at a time different from the time when the differential amplification operation of said cross-coupled P-channel MISFETs is started; and

precharging means for setting said pair of data lines at a potential intermediate between potentials on said pair of data lines obtained by operating said amplifier means after said selecting means places said plurality of memory cells in a non-selected state.

2. A semiconductor memory according to claim 1, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cell.