Non-volatile memory cell having Si rich silicon nitride charge trapping layer

• US 4,870,470 A
• Filed: 10/16/1987
• Issued: 09/26/1989
• Est. Priority Date: 10/16/1987
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bass, Roy S. Jr., Bhattacharyya, Arup, Grise, Gary D.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/108,886
• Time in Patent Office: 711 Days
• Field of Search: 357/23.5, 357/23.15, 357/54, 357/49, 357/45
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

Claims

1. A charge storage means for a memory cell comprising a layer of silicon-rich silicon nitride having an index of refraction between approximately 2.10 and 2.35, and a thickness of less than 90 nm, so that said layer of silicon-rich silicon nitride provides appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichimetric silicon nitride.

2. The memory cell as recited in claim 1, wherein said layer of silicon-rich silicon nitride is chemical vapor deposited from a silane-based source and an ammonia source, so that silane and ammonia are introduced at a flow rate ratio of between approximately 3:

1 and 10;

1, respectively.

3. An memory cell comprising a field effect transistor having source, gate, and drain electrodes, said gate electrode including a gate stack comprising:

a dielectric structure deposited on the substrate between said source and drain electrodes;

a first layer of silicon-rich silicon nitride disposed on said dielectric structure, said first layer of silicon-rich silicon nitride having an index of refraction of less than 2.35;

a barrier structure disposed on said first layer of silicon-rich silicon nitride;

a second layer of silicon-rich silicon nitride disposed on said barrier structure, said second layer of silicon-rich silicon nitride having an index of refraction of at least 2.35; and

a control electrode disposed on said second silicon-rich silicon nitride layer.

4. The memory cell as recited in claim 3, wherein said dielectric structure is comprised of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

5. The memory cell as recited in claim 3, wherein said barrier structure comprises a layer of thermally grown silicon oxide.

6. The memory cell as recited in claim 3, wherein said control electrode is comprised of a material selected from the group consisting of doped polysilicon, aluminum, aluminum alloys, refractory metals, refractory metal silicides, and combinations thereof.

7. A memory cell formed on a semiconductor substrate, comprising:

a gate stack, comprising

a first dielectric structure formed on a first portion of the substrate,

a first silicon-rich silicon nitride layer having an index of refraction of less than 2.35 disposed on said first dielectric structure, said first silicon-rich silicon nitride layer having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride,

a second dielectric structure disposed on said first silicon-rich silicon nitride layer,

a second layer of silicon-rich silicon nitride disposed on said second dielectric structure, said second silicon-rich silicon nitride layer having an index of refraction of at least 2.35, said second silicon-rich silicon nitride layer having sufficient excess silicon to provide appreciable charge injection enhancement as compared to stoichiometric silicon nitride;

a control electrode disposed on said second layer of silicon-rich silicon nitride;

first and second diffusion regions formed in portions of said substrate abutting said first portion of the substrate;

first means for biasing said first diffusion region; and

second means independent of said first means for biasing said second diffusion region.

8. The memory cell as recited in claim 7, wherein said first dielectric structure comprises thermally grown silicon oxide.

9. The memory cell as recited in claim 7, wherein said second dielectric structure comprises thermally grown silicon oxide.

10. The memory cell as recited in claim 7, wherein said control electrode is comprised of doped polysilicon.

11. The memory cell as recited in claim 7, wherein said first means comprises a first metal line that contacts said first diffusion region through a first via formed in a passivation layer coated on the substrate, and wherein said second means comprises a second metal line that contacts said second diffusion region through a second via formed in a passivation layer coated on the substrate.

12. An array of memory cells formed on a semiconductor substrate, comprising:

isolation means formed in the substrate for defining discrete portions of the substrate that are isolated from remaining portions of the substrate;

a plurality of cells being formed in each of said isolated discrete portions of the substrate, each of said cells comprising an FET having source and drain diffusions formed in the substrate and a gate electrode formed on a portion of the substrate between said source and drain diffusions,

said gate electrode comprising a dielectric structure formed on the substrate, a first layer of silicon-rich silicon nitride having an index of refraction between approximately 2.10 and 2.30, said first layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, a barrier structure, and a control electrode;

first means for biasing said source diffusions;

second means for biasing said drain diffusions; and

third means for biasing each of said isolated discrete portions of said substrate separately from others of said isolated discrete portions of said substrate.

13. The array as recited in claim 12, wherein said isolation means comprises a plurality of spaced trenches that are filled with one or more isolation materials.

14. The array as recited in claim 13, wherein each of said trenches have sidewalls and a bottom that are coated with a dielectric material.

15. The array as recited in claim 14, wherein said dielectric material comprises silicon oxide.

16. The array as recited in claim 14, wherein said trenches are filled with a semiconductive material.

17. The array as recited in claim 16, wherein said semiconductive material comprises polysilicon.

18. The array as recited in claim 14, wherein said dielectric material fills said trenches.

19. The array as recited in claim 12, wherein said gate electrode further comprises a charge injection means disposed between said barrier structure and said control electrode.

20. The array as recited in claim 19, wherein said charge injection means comprises a second layer of silicon-rich silicon nitride having an index of refraction of at least 2.35, said second layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge conductance enhancement as compared to stoichiometric silicon nitride.

21. The array as recited in claim 20, wherein said first layer of silicon-rich silicon nitride, said barrier structure, and said second layer of silicon-rich silicon nitride are formed on only a first portion of said dielectric structure, and wherein said control electrode is formed over both said second layer of silicon-rich silicon nitride and remaining portions of said dielectric structure.

22. The array as recited in claim 20, wherein said first layer of silicon nitride has an index of refraction between approximately 2.10 and 2.17, and wherein said second layer of silicon nitride has an index of refraction of approximately 2.50.

23. The array as recited in claim 12, wherein said first means for biasing comprises a first series of conductive lines coupled to a first series of voltages sources, respectively, each one of said first conductive lines being coupled to respective source diffusions of said cells formed in a respective one of said isolated discrete portion of said substrate.

24. The array as recited in claim 23, wherein said second means for biasing comprises a second series of conductive lines coupled to a second series of voltage sources, respectively, each one of said second conductive lines being coupled to respective drain diffusions of said cells formed in a respective one of said isolated discrete portions of said substrate.