Parallel neural network for a full binary adder

• US 4,891,782 A
• Filed: 12/17/1987
• Issued: 01/02/1990
• Est. Priority Date: 12/17/1987
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Army (Government of the United States of America)
• Original Assignee: United States Of America As Represented By The Secretary Of The Army (Government of the United States of America)
• Inventors: Johnson, John L.
• Primary Examiner(s): Clark, David L.
• Assistant Examiner(s): Mai, Tan V.
• Application Number:
  US07/135,404
• Time in Patent Office: 747 Days
• Field of Search: 364/760, 364/784, 364/786, 307/201, 360/146.2, 371/21
• US Class Current: 708/706
• CPC Class Codes: G06F 2207/4802 Special implementations
• CPC Class Codes: G06F 7/4991 Overflow or underflow
• CPC Class Codes: G06F 7/505 in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
• CPC Class Codes: G06N 3/044 Recurrent networks, e.g. Hopfield networks
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A method for performing the addition of two N-bit binary numbers using palel neural networks. The value of a first register is converted and transferred into a second register in a mathematical fashion so as to add the numbers of the first register into the second register. When the first register contains all zeros then the desired sum is found in the second register.

Claims

1. A method for adding a first binary number to a second binary number wherein said first binary number is contained in a first register and said second binary number is contained in a second register comprising the steps of (A) comparing the same significant bit of each of the bits of said first and second registers and only when said first register has a one value and said second register has a zero value, changing the one value in the first register to a zero value and the zero value in the second register to a one value;

(B) comparing the same significant bit of each of the first and second registers and the next higher significant bit of said first register, and only when the next higher significant bit has a value of zero and the other bits have a one value, changing the zero value to a one value and the one values to zero values; and

(C) repeating steps A and B until the first register has all zero values whereby the second register contains the digital sum of said first and second registers.

2. A method as set forth in claim 1 further comprising the step of performing steps A and B as parallel operations the first time and each repeated time.

3. A method as set forth in claim 2 wherein said first register further has an overflow bin which is regarded for the purposes of step B as the most significant bit plus one of the first register;

and said overflow bin considered as the most significant bit plus one of the second register for determining when the first register has all zeros and for determining the digital sum of said first and second digital numbers.